Cite this DOI

Subramanian, A. S., Priya Dharshini, R., R.siranjeevi, & S.Joshua smith (2018). A Novel Reduced Switch Multilevel Inverter Using FPGA. *Journal of Science & Technology*, *03*(03), 12–16. https://doi.org/10.46243/jstj.2018.v3.i3.174

@article{subramanian2018novel,
  author    = {Subramanian, A.T. Sankara and Priya Dharshini, R.Sooriya and R.siranjeevi and S.Joshua smith},
  title     = {{A Novel Reduced Switch Multilevel Inverter Using FPGA}},
  journal   = {Journal of Science \& Technology},
  year      = {2018},
  month     = {may},
  volume    = {03},
  number    = {03},
  pages     = {12--16},
  publisher = {Longman Publishers},
  issn      = {2456-5660},
  doi       = {10.46243/jstj.2018.v3.i3.174},
  url       = {https://doi.org/10.46243/jstj.2018.v3.i3.174},
  language  = {en},
  abstract  = {Multilevel inverters (MLI) are mostly used medium -voltage and high -power applications due to its attractive features. As the number of output voltage levels increases, the quality of the output voltage is improved leading to reduction of the filtering requirements. But multilevel inverter requires more number of power semicond uctor switches as number of levels increase that increases cost and complexity in control circuit. In this paper, an innovative topology for multilevel inverter is proposed which reduces the number of switches considerably without increasing the total stan ding voltage of the switches. The proposed topology is a general topology which can be extended for any number of voltage levels. This topology as reduced switch multilevel inverter, we implement and generate the PWM by FPGA Spartron3E processor using VHDL language}
}

TY  - JOUR
TI  - A Novel Reduced Switch Multilevel Inverter Using FPGA
AU  - Subramanian, A.T. Sankara
AU  - Priya Dharshini, R.Sooriya
AU  - R.siranjeevi
AU  - S.Joshua smith
JO  - Journal of Science & Technology
PY  - 2018
DA  - 2018/05/04/
VL  - 03
IS  - 03
SP  - 12
EP  - 16
PB  - Longman Publishers
SN  - 2456-5660
LA  - en
AB  - Multilevel inverters (MLI) are mostly used medium -voltage and high -power applications due to its attractive features. As the number of output voltage levels increases, the quality of the output voltage is improved leading to reduction of the filtering requirements. But multilevel inverter requires more number of power semicond uctor switches as number of levels increase that increases cost and complexity in control circuit. In this paper, an innovative topology for multilevel inverter is proposed which reduces the number of switches considerably without increasing the total stan ding voltage of the switches. The proposed topology is a general topology which can be extended for any number of voltage levels. This topology as reduced switch multilevel inverter, we implement and generate the PWM by FPGA Spartron3E processor using VHDL language
DO  - 10.46243/jstj.2018.v3.i3.174
UR  - https://doi.org/10.46243/jstj.2018.v3.i3.174
ER  -

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    "id": "10.46243/jstj.2018.v3.i3.174",
    "DOI": "10.46243/jstj.2018.v3.i3.174",
    "URL": "https://doi.org/10.46243/jstj.2018.v3.i3.174",
    "title": "A Novel Reduced Switch Multilevel Inverter Using FPGA",
    "source": "Smart Scholars DOI Registry",
    "container-title": "Journal of Science & Technology",
    "author": [
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    "volume": "03",
    "issue": "03",
    "page": "12-16",
    "publisher": "Longman Publishers",
    "language": "en",
    "abstract": "Multilevel inverters (MLI) are mostly used medium -voltage and high -power applications due to its attractive features. As the number of output voltage levels increases, the quality of the output voltage is improved leading to reduction of the filtering requirements. But multilevel inverter requires more number of power semicond uctor switches as number of levels increase that increases cost and complexity in control circuit. In this paper, an innovative topology for multilevel inverter is proposed which reduces the number of switches considerably without increasing the total stan ding voltage of the switches. The proposed topology is a general topology which can be extended for any number of voltage levels. This topology as reduced switch multilevel inverter, we implement and generate the PWM by FPGA Spartron3E processor using VHDL language",
    "ISSN": "2456-5660"
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From the record as registered (version 2) — the record and its history. Programs: https://registry.smartscholars.in/api.php?action=cite&doi=10.46243%2Fjstj.2018.v3.i3.174 gives all four in one JSON answer.