Cite this DOI

K.G.VENKATA KRISHNA, ANUSHA BATHALA, ASIRI NAIDU KOYYANA, & VAMSI KRISHNA REDDY.S (2025). DESIGN AND ANALYSIS OF 32 – BIT HIGH SPEED RISC PROCESSOR USING PIPELINING TECHNIQUE. *Journal of Science & Technology*, *10*(4), 34–44. https://doi.org/10.46243/jst.2025.v10.i04.pp34-44

@article{kgvenkatakrishna2025design,
  author    = {K.G.VENKATA KRISHNA and ANUSHA BATHALA and ASIRI NAIDU KOYYANA and VAMSI KRISHNA REDDY.S},
  title     = {{DESIGN AND ANALYSIS OF 32 – BIT HIGH SPEED RISC PROCESSOR USING PIPELINING TECHNIQUE}},
  journal   = {Journal of Science \& Technology},
  year      = {2025},
  month     = {apr},
  volume    = {10},
  number    = {4},
  pages     = {34--44},
  publisher = {Longman Publishers},
  issn      = {2456-5660},
  doi       = {10.46243/jst.2025.v10.i04.pp34-44},
  url       = {https://doi.org/10.46243/jst.2025.v10.i04.pp34-44},
  abstract  = {The Reduced Instruction Set Computer (RISC) architecture prioritizes a compact, efficient set ofinstructions that execute in uniform cycles, enabling high-performance computing across devices—fromembedded systems to supercomputers. This research presents the design and implementation of a 32-bitRISC processor leveraging a pipelining technique to enhance throughput while maintainingcomputational efficiency. The proposed processor supports 16 arithmetic and logical operations andadheres to the Harvard architecture, featuring separate data and instruction memories for concurrent access.The processor incorporates a 32-bit ALU for arithmetic and logical computations, alongwith general-purpose registers and a dedicated flag register to track carry, zero, andparity statuses. The pipelined design divides instruction execution into multiple stages(fetch, decode, execute, memory access, and write-back), significantly improvinginstruction throughput. Each instruction is encoded uniformly, and the design supportsmultiple addressing modes for flexibility.}
}

TY  - JOUR
TI  - DESIGN AND ANALYSIS OF 32 – BIT HIGH SPEED RISC PROCESSOR USING PIPELINING TECHNIQUE
AU  - K.G.VENKATA KRISHNA
AU  - ANUSHA BATHALA
AU  - ASIRI NAIDU KOYYANA
AU  - VAMSI KRISHNA REDDY.S
JO  - Journal of Science & Technology
PY  - 2025
DA  - 2025/04/25/
VL  - 10
IS  - 4
SP  - 34
EP  - 44
PB  - Longman Publishers
SN  - 2456-5660
AB  - The Reduced Instruction Set Computer (RISC) architecture prioritizes a compact, efficient set ofinstructions that execute in uniform cycles, enabling high-performance computing across devices—fromembedded systems to supercomputers. This research presents the design and implementation of a 32-bitRISC processor leveraging a pipelining technique to enhance throughput while maintainingcomputational efficiency. The proposed processor supports 16 arithmetic and logical operations andadheres to the Harvard architecture, featuring separate data and instruction memories for concurrent access.The processor incorporates a 32-bit ALU for arithmetic and logical computations, alongwith general-purpose registers and a dedicated flag register to track carry, zero, andparity statuses. The pipelined design divides instruction execution into multiple stages(fetch, decode, execute, memory access, and write-back), significantly improvinginstruction throughput. Each instruction is encoded uniformly, and the design supportsmultiple addressing modes for flexibility.
DO  - 10.46243/jst.2025.v10.i04.pp34-44
UR  - https://doi.org/10.46243/jst.2025.v10.i04.pp34-44
ER  -

{
    "type": "article-journal",
    "id": "10.46243/jst.2025.v10.i04.pp34-44",
    "DOI": "10.46243/jst.2025.v10.i04.pp34-44",
    "URL": "https://doi.org/10.46243/jst.2025.v10.i04.pp34-44",
    "title": "DESIGN AND ANALYSIS OF 32 – BIT HIGH SPEED RISC PROCESSOR USING PIPELINING TECHNIQUE",
    "source": "Smart Scholars DOI Registry",
    "container-title": "Journal of Science & Technology",
    "author": [
        {
            "family": "K.G.VENKATA KRISHNA"
        },
        {
            "family": "ANUSHA BATHALA"
        },
        {
            "family": "ASIRI NAIDU KOYYANA"
        },
        {
            "family": "VAMSI KRISHNA REDDY.S"
        }
    ],
    "issued": {
        "date-parts": [
            [
                2025,
                4,
                25
            ]
        ]
    },
    "volume": "10",
    "issue": "4",
    "page": "34-44",
    "publisher": "Longman Publishers",
    "abstract": "The Reduced Instruction Set Computer (RISC) architecture prioritizes a compact, efficient set ofinstructions that execute in uniform cycles, enabling high-performance computing across devices—fromembedded systems to supercomputers. This research presents the design and implementation of a 32-bitRISC processor leveraging a pipelining technique to enhance throughput while maintainingcomputational efficiency. The proposed processor supports 16 arithmetic and logical operations andadheres to the Harvard architecture, featuring separate data and instruction memories for concurrent access.The processor incorporates a 32-bit ALU for arithmetic and logical computations, alongwith general-purpose registers and a dedicated flag register to track carry, zero, andparity statuses. The pipelined design divides instruction execution into multiple stages(fetch, decode, execute, memory access, and write-back), significantly improvinginstruction throughput. Each instruction is encoded uniformly, and the design supportsmultiple addressing modes for flexibility.",
    "ISSN": "2456-5660"
}

From the record as registered (version 2) — the record and its history. Programs: https://registry.smartscholars.in/api.php?action=cite&doi=10.46243%2Fjst.2025.v10.i04.pp34-44 gives all four in one JSON answer.