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Cite this DOI

10.46243/jst.2022.v7.i02.pp21-29 · A comparative analysis of 128 bytes SRAM architecture using Single ended three and six transistor SRAM cells

APA (7th edition)

B.N. Srinivasarao, B. S. (2022). A comparative analysis of 128 bytes SRAM architecture using Single ended three and six transistor SRAM cells. *Journal of Science & Technology*, *7*(2), 21–29. https://doi.org/10.46243/jst.2022.v7.i02.pp21-29

⬇ text Italics are shown as *asterisks* in plain text — the journal or book title and the volume.

BibTeX

@article{bnsrinivasarao2022comparative,
  author    = {B.N. Srinivasarao, B.N. Srinivasarao},
  title     = {{A comparative analysis of 128 bytes SRAM architecture using Single ended three and six transistor SRAM cells}},
  journal   = {Journal of Science \& Technology},
  year      = {2022},
  month     = {jul},
  volume    = {7},
  number    = {2},
  pages     = {21--29},
  publisher = {Longman Publishers},
  issn      = {2456-5660},
  doi       = {10.46243/jst.2022.v7.i02.pp21-29},
  url       = {https://doi.org/10.46243/jst.2022.v7.i02.pp21-29},
  language  = {en},
  abstract  = {Static RAM architecture is an important part in the digital data processing devices like DSP’s Micro Processors and Embedded systems for general purpose or specific purpose applications. Demand of manufacturing compact devices are increasing day by day, to make the compact devices the design of internal circuits area also should be reduced. This will in turn reduces the overall size of the device. In this paper two 128 bytes SRAM architectures are implemented with conventional six transistors SRAM cell and single ended three transistor SRAM cell from the scratch to layout level. The designs are compared in terms of power consumption, area, and speed with 45nm technology. The implemented design area is reduced by 57.14\% with 92.37\% reduced power consumption and with 89.98\% improved performance.}
}

⬇ .bib

RIS (EndNote, Zotero, Mendeley)

TY  - JOUR
TI  - A comparative analysis of 128 bytes SRAM architecture using Single ended three and six transistor SRAM cells
AU  - B.N. Srinivasarao, B.N. Srinivasarao
JO  - Journal of Science & Technology
PY  - 2022
DA  - 2022/07/03/
VL  - 7
IS  - 2
SP  - 21
EP  - 29
PB  - Longman Publishers
SN  - 2456-5660
LA  - en
AB  - Static RAM architecture is an important part in the digital data processing devices like DSP’s Micro Processors and Embedded systems for general purpose or specific purpose applications. Demand of manufacturing compact devices are increasing day by day, to make the compact devices the design of internal circuits area also should be reduced. This will in turn reduces the overall size of the device. In this paper two 128 bytes SRAM architectures are implemented with conventional six transistors SRAM cell and single ended three transistor SRAM cell from the scratch to layout level. The designs are compared in terms of power consumption, area, and speed with 45nm technology. The implemented design area is reduced by 57.14% with 92.37% reduced power consumption and with 89.98% improved performance.
DO  - 10.46243/jst.2022.v7.i02.pp21-29
UR  - https://doi.org/10.46243/jst.2022.v7.i02.pp21-29
ER  -

⬇ .ris

CSL-JSON

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    "type": "article-journal",
    "id": "10.46243/jst.2022.v7.i02.pp21-29",
    "DOI": "10.46243/jst.2022.v7.i02.pp21-29",
    "URL": "https://doi.org/10.46243/jst.2022.v7.i02.pp21-29",
    "title": "A comparative analysis of 128 bytes SRAM architecture using Single ended three and six transistor SRAM cells",
    "source": "Smart Scholars DOI Registry",
    "container-title": "Journal of Science & Technology",
    "author": [
        {
            "family": "B.N. Srinivasarao",
            "given": "B.N. Srinivasarao"
        }
    ],
    "issued": {
        "date-parts": [
            [
                2022,
                7,
                3
            ]
        ]
    },
    "volume": "7",
    "issue": "2",
    "page": "21-29",
    "publisher": "Longman Publishers",
    "language": "en",
    "abstract": "Static RAM architecture is an important part in the digital data processing devices like DSP’s Micro Processors and Embedded systems for general purpose or specific purpose applications. Demand of manufacturing compact devices are increasing day by day, to make the compact devices the design of internal circuits area also should be reduced. This will in turn reduces the overall size of the device. In this paper two 128 bytes SRAM architectures are implemented with conventional six transistors SRAM cell and single ended three transistor SRAM cell from the scratch to layout level. The designs are compared in terms of power consumption, area, and speed with 45nm technology. The implemented design area is reduced by 57.14% with 92.37% reduced power consumption and with 89.98% improved performance.",
    "ISSN": "2456-5660"
}

⬇ .json What citeproc and reference managers read; the DOI system hands it out for Accept: application/vnd.citationstyles.csl+json, and so does this registry's resolver.

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