{ "ok": true, "doi": "10.46243/jst.2025.v10.i04.pp34-44", "doi_display": "10.46243/jst.2025.v10.i04.pp34-44", "doi_url": "https://doi.org/10.46243/jst.2025.v10.i04.pp34-44", "state": "registered", "url": "https://jst.org.in/index.php/pub/article/view/1243", "title": "DESIGN AND ANALYSIS OF 32 – BIT HIGH SPEED RISC PROCESSOR USING PIPELINING TECHNIQUE", "version": 2, "registered_via": "crossref", "prefix": { "prefix": "10.46243", "status": "live" }, "registrant": { "name": "Longman Publishers", "kind": "publisher", "country": "India" }, "reserved_at": null, "registered_at": "2026-09-29 22:00:32", "updated_at": "2026-09-29 23:59:51", "withdrawn_at": null, "withdrawn_reason": null, "record": { "format": "smartscholars-doi-metadata/1.0", "doi": "10.46243/jst.2025.v10.i04.pp34-44", "referent": "Creation", "type": "JournalArticle", "structural_type": "Digital", "modes": [ "Visual" ], "characters": [ "Language" ], "titles": [ { "value": "DESIGN AND ANALYSIS OF 32 – BIT HIGH SPEED RISC PROCESSOR USING PIPELINING TECHNIQUE", "type": "PrincipalTitle" } ], "identifiers": [ { "type": "DOI", "value": "10.46243/jst.2025.v10.i04.pp34-44" } ], "agents": [ { "role": "author", "name": { "given": "", "family": "K.G.VENKATA KRISHNA" }, "sequence": "first" }, { "role": "author", "name": { "given": "", "family": "ANUSHA BATHALA" }, "sequence": "additional" }, { "role": "author", "name": { "given": "", "family": "ASIRI NAIDU KOYYANA" }, "sequence": "additional" }, { "role": "author", "name": { "given": "", "family": "VAMSI KRISHNA REDDY.S" }, "sequence": "additional" }, { "role": "publisher", "name": { "org": "Longman Publishers" } } ], "dates": { "published": "2025-04-25", "date_type": "PublicationDate", "online": "2025-04-25" }, "container": { "type": "Journal", "titles": [ { "value": "Journal of Science & Technology", "type": "PrincipalTitle" }, { "value": "J. sci. technol.", "type": "AbbreviatedTitle" } ], "identifiers": [ { "type": "ISSN", "value": "2456-5660", "medium": "electronic" } ], "volume": "10", "issue": "4", "pages": { "first": "34", "last": "44" } }, "links": [ { "url": "https://jst.org.in/index.php/pub/article/view/1243", "return_type": "text/html", "primary": true }, { "url": "https://jst.org.in/index.php/pub/article/download/1243/982", "purpose": "text-mining", "return_type": "application/pdf" } ], "abstract": { "value": "The Reduced Instruction Set Computer (RISC) architecture prioritizes a compact, efficient set ofinstructions that execute in uniform cycles, enabling high-performance computing across devices—fromembedded systems to supercomputers. This research presents the design and implementation of a 32-bitRISC processor leveraging a pipelining technique to enhance throughput while maintainingcomputational efficiency. The proposed processor supports 16 arithmetic and logical operations andadheres to the Harvard architecture, featuring separate data and instruction memories for concurrent access.The processor incorporates a 32-bit ALU for arithmetic and logical computations, alongwith general-purpose registers and a dedicated flag register to track carry, zero, andparity statuses. The pipelined design divides instruction execution into multiple stages(fetch, decode, execute, memory access, and write-back), significantly improvinginstruction throughput. Each instruction is encoded uniformly, and the design supportsmultiple addressing modes for flexibility." }, "license": { "url": "https://creativecommons.org/licenses/by/4.0", "start": "2025-04-25", "applies_to": "unspecified" }, "references": [ { "key": "ref1", "doi": "10.1109/iccubea47591.2019.9128517", "unstructured": "S. Lad and V. S. Bendre, “Design and Comparison of Multiplier using Vedic Sutras,” 2019 5th International Conference On Computing, Communication, Control And Automation (ICCUBEA), Pune, India, 2019, pp. 1-5" }, { "key": "ref2", "unstructured": "Balpande Vishwas V, Abhishek B. Pande, Meeta J. Walke, Bhavna D. Choudhari and Kiran R. Bagade. “Design and Implementation of 16 Bit Processor on FPGA.” (2015)" }, { "key": "ref3", "doi": "10.1109/socdc.2008.4815726", "unstructured": "Seung Pyo Jung, Jingzhe Xu, Donghoon Lee, Ju Sung Park, Kang-joo Kim and Koon- shik Cho, “Design & verification of 16 bit RISC processor,” 2008 International SoC Design Conference, Busan, 2008, pp. III-13-III-14, doi: 10.1109/ SOCDC.2008.4815726" }, { "key": "ref4", "doi": "10.1109/icaccct.2014.7019410", "unstructured": "A. Bisoyi, M. Baral and M. K. Senapati, “Comparison of a 32-bit Vedic multiplier with a conventional binary multiplier,” 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies, Ramanathapuram, 2014, pp. 1757- 1760, doi: 10.1109/ICACCCT.2014.7019410" }, { "key": "ref5", "doi": "10.5120/16742-6956", "unstructured": "Mr. Nishant G. Deshpande, Prof. Rashmi Mahajan, “Ancient Indian Vedic Mathematics based Multiplier Design for High Speed and Low Power Processor”, IJAREEIE, Pune, 2014" }, { "key": "ref6", "unstructured": "Priyanka jain, Dr. G. S. Virdi, : Multiplier-Accumulator (MAC) Unit: International Journal of Digital Application & Contemporary Research,Volume 5, Issue 3, October 2016" }, { "key": "ref7", "doi": "10.1109/icit.2006.372448", "unstructured": "P. S. Mane, I. Gupta and M. K. Vasantha, “Implementation of RISC Processor on FPGA,” 2006 IEEE International Conference on Industrial Technology, Mumbai, 2006, pp. 2096- 2100, doi: 10.1109/ICIT.2006.372448" }, { "key": "ref8", "doi": "10.1109/iccpct.2016.7530294", "unstructured": "Ram, G. & Lakshmanna, Y. & Rani, D. & Kandula, Bala. (2016). Area efficient modified vedic multiplier. 1-5. 10.1109/ ICCPCT.2016.7530294" }, { "key": "ref9", "unstructured": "Yogesh M. Motey, Tejaswini G. Panse, “Traditional and Truncation Schemes for Different Multipliers”, International Journal of Electronics and Computer Science Engineering, vol.2, no.2, pp.627-633, May 2013" } ], "record": { "registrant": "Longman Publishers", "registered": "2025-08-26", "updated": "2026-09-07", "issue_number": 1, "source": "crossref-api", "source_agency": "Crossref (member 25296)" } }, "record_sha256": "a1a35c00ccd0a2f817de63130a4d217727f0ddf80072b4a1e118b7adb6fdd904", "handle": { "synced_at": "2026-10-01 18:12:54", "url": "https://jst.org.in/index.php/pub/article/view/1243" }, "links": { "record_page": "https://registry.smartscholars.in/record.php?doi=10.46243%2Fjst.2025.v10.i04.pp34-44", "system_metadata": "https://registry.smartscholars.in/resolve.php?doi=10.46243%2Fjst.2025.v10.i04.pp34-44&as=system", "history": "https://registry.smartscholars.in/api.php?action=history&doi=10.46243%2Fjst.2025.v10.i04.pp34-44", "kernel_xml": "https://registry.smartscholars.in/resolve.php?doi=10.46243%2Fjst.2025.v10.i04.pp34-44&as=xml" } }