{ "ok": true, "doi": "10.46243/jst.2024.v9.i4.pp50-58", "doi_display": "10.46243/jst.2024.v9.i4.pp50-58", "doi_url": "https://doi.org/10.46243/jst.2024.v9.i4.pp50-58", "state": "registered", "url": "https://www.jst.org.in/index.php/pub/article/view/1056", "title": "A Comprehensive Analysis of 32nmtechnology of Ladner Fischer Adder usingCMOSLogic,PTL,andDPTLFocusing onPower", "version": 2, "registered_via": "crossref", "prefix": { "prefix": "10.46243", "status": "live" }, "registrant": { "name": "Longman Publishers", "kind": "publisher", "country": "India" }, "reserved_at": null, "registered_at": "2026-09-29 22:00:41", "updated_at": "2026-09-30 00:00:01", "withdrawn_at": null, "withdrawn_reason": null, "record": { "format": "smartscholars-doi-metadata/1.0", "doi": "10.46243/jst.2024.v9.i4.pp50-58", "referent": "Creation", "type": "JournalArticle", "structural_type": "Digital", "modes": [ "Visual" ], "characters": [ "Language" ], "titles": [ { "value": "A Comprehensive Analysis of 32nmtechnology of Ladner Fischer Adder usingCMOSLogic,PTL,andDPTLFocusing onPower", "type": "PrincipalTitle", "lang": "en" } ], "identifiers": [ { "type": "DOI", "value": "10.46243/jst.2024.v9.i4.pp50-58" } ], "agents": [ { "role": "author", "name": { "given": "", "family": "K.Srilatha" }, "sequence": "first" }, { "role": "author", "name": { "given": "K.SriLakshmi", "family": "Amulya" }, "sequence": "additional" }, { "role": "author", "name": { "given": "G.Amara", "family": "Sowjanya" }, "sequence": "additional" }, { "role": "author", "name": { "given": "", "family": "M.Hima" }, "sequence": "additional" }, { "role": "publisher", "name": { "org": "Longman Publishers" } } ], "dates": { "published": "2024-04-01", "date_type": "PublicationDate", "online": "2024-04-01" }, "language": "en", "container": { "type": "Journal", "titles": [ { "value": "Journal of Science & Technology", "type": "PrincipalTitle" } ], "identifiers": [ { "type": "ISSN", "value": "2456-5660", "medium": "electronic" } ], "volume": "09", "issue": "04", "pages": { "first": "50", "last": "58" } }, "links": [ { "url": "https://www.jst.org.in/index.php/pub/article/view/1056", "return_type": "text/html", "primary": true }, { "url": "https://www.jst.org.in/index.php/pub/article/download/1056/923", "purpose": "text-mining", "return_type": "application/pdf" }, { "url": "https://www.jst.org.in/index.php/pub/article/download/1056/4012", "purpose": "text-mining", "return_type": "application/xml" }, { "url": "https://www.jst.org.in/index.php/pub/article/view/1056/923", "purpose": "similarity-checking" } ], "abstract": { "value": "Adders are designed as essential components in digital signal processing and VLSI technologies. Among them, parallel prefix adders offer significant speed advantages over traditional binary adders for various electronic applications. This paper explores the design of a 4-bit Ladner-Fischer adder using different technologies like CMOS, pass transistor logic, and double pass transistor logic to achieve a more efficient use of low power. These implementation results demonstrate that the Ladner Fischer adder, designed with CMOS, PTL, and DPTL, has reduced power consumption The simulation was performed using Dsch3 and the Microwind 3.1 tool.", "lang": "en" }, "license": { "url": "https://creativecommons.org/licenses/by/4.0/", "start": "2024-04-01", "applies_to": "vor" }, "references": [ { "key": "ref1", "doi": "10.1109/iconstem56934.2023.10142406", "unstructured": "“An Efficient Design and Performance Analysis ofNovel 8 Bit Modified Wallace Multiplier Using KoggeStone Adder (KSA) in Comparison with Ripple carry adder(RCA)”. (IEEE Access, 2023)" }, { "key": "ref2", "unstructured": "“Design and Parametric Evaluation of Kogge Stone Adder using CMOS and PTL in terms of Delay AND Area”.(Published in June 2022)" }, { "key": "ref3", "unstructured": "“Analysis of Parallel Prefix Adders with Low Power andHigher Speed “. (Published in 2022)" }, { "key": "ref4", "doi": "10.1109/icicv50876.2021.9388489", "unstructured": "”Design an Area Efficient Kogge Stone Adder using Pass Transistor Logic “. (Published in March 2021)" }, { "key": "ref5", "doi": "10.1109/iccs1.2017.8325971", "unstructured": "S. Daphni and K. S. V. Grace, “A review analysis of parallel prefix adders for better performance in VLSI applications,” 2017 IEEE International Conference on Circuits and Systems (ICCS), 2017,pp. 103-106" }, { "key": "ref6", "unstructured": "Ahmet SERTBAS and R. Selami OZBEY, “APerformance analysis of classified binary adderarchitectures and the VHDL Simulations”, Journal of Electrical & Electronics Engineering,2004, vol:4, PP:1025-1030" }, { "key": "ref7", "doi": "10.25046/aj040213", "unstructured": "S. Daphni, K. S. Vijula Grace, “Design andAnalysis of 32-bit Parallel Adders for Low Power VLSIApplications” in Advance in Science, Technology andEngineering Systems Journal Vol. 4, No. 2, PP: 102-106(2019)" }, { "key": "ref8", "doi": "10.1109/cicn.2016.117", "unstructured": "C. N. Shilpa, K. D. Shinde and H. V. Nithin, “Design, Implementation and Comparative Analysis of Kogge Stone Adder Using CMOS and GDI Design:A VLSI Based Approach,” 2016 8th International Conference on Computational Intelligence and Communication Networks (CICN), 2016, pp.570-574" }, { "key": "ref9", "doi": "10.1109/icdcsyst.2018.8605064", "unstructured": "R. M. James and A. Ravindran, “Review of Full Adder Performance Analysis Using Kogge Stone Adder and Magnetic Tunnel Junction,” 2018 4th International Conference on Devices, Circuits andSystems (ICDCS), 2018, pp. 8490" }, { "key": "ref10", "doi": "10.1016/b978-0-12-415992-1.00009-2", "unstructured": "B. David, Kirk Wen-mei W. Hwu, “Chapter 9–Parallel Patterns: Prefix Sum: An Introduction to Work Efficiency in Parallel Algorithms”, in Programming Massively Parallel Processors (SecondEdition), PP: 197-216(2013)" } ], "record": { "registrant": "Longman Publishers", "registered": "2026-09-18", "updated": "2026-09-21", "issue_number": 1, "source": "crossref-api", "source_agency": "Crossref (member 25296)" } }, "record_sha256": "cf7d50bae6eb7133f7c6ad2bc0fb1898f7e847d0ad04cfb0e5de01189040c891", "handle": { "synced_at": "2026-10-01 18:14:02", "url": "https://www.jst.org.in/index.php/pub/article/view/1056" }, "links": { "record_page": "https://registry.smartscholars.in/record.php?doi=10.46243%2Fjst.2024.v9.i4.pp50-58", "system_metadata": "https://registry.smartscholars.in/resolve.php?doi=10.46243%2Fjst.2024.v9.i4.pp50-58&as=system", "history": "https://registry.smartscholars.in/api.php?action=history&doi=10.46243%2Fjst.2024.v9.i4.pp50-58", "kernel_xml": "https://registry.smartscholars.in/resolve.php?doi=10.46243%2Fjst.2024.v9.i4.pp50-58&as=xml" } }