{
    "ok": true,
    "doi": "10.46243/jst.2022.v7.i02.pp21-29",
    "doi_display": "10.46243/jst.2022.v7.i02.pp21-29",
    "doi_url": "https://doi.org/10.46243/jst.2022.v7.i02.pp21-29",
    "state": "registered",
    "url": "https://www.jst.org.in/index.php/pub/article/view/253",
    "title": "A comparative analysis of 128 bytes SRAM architecture using Single ended three and six transistor SRAM cells",
    "version": 2,
    "registered_via": "crossref",
    "prefix": {
        "prefix": "10.46243",
        "status": "live"
    },
    "registrant": {
        "name": "Longman Publishers",
        "kind": "publisher",
        "country": "India"
    },
    "reserved_at": null,
    "registered_at": "2026-09-29 22:00:27",
    "updated_at": "2026-09-29 23:59:46",
    "withdrawn_at": null,
    "withdrawn_reason": null,
    "record": {
        "format": "smartscholars-doi-metadata/1.0",
        "doi": "10.46243/jst.2022.v7.i02.pp21-29",
        "referent": "Creation",
        "type": "JournalArticle",
        "structural_type": "Digital",
        "modes": [
            "Visual"
        ],
        "characters": [
            "Language"
        ],
        "titles": [
            {
                "value": "A comparative analysis of 128 bytes SRAM architecture using Single ended three and six transistor SRAM cells",
                "type": "PrincipalTitle",
                "lang": "en"
            }
        ],
        "identifiers": [
            {
                "type": "DOI",
                "value": "10.46243/jst.2022.v7.i02.pp21-29"
            }
        ],
        "agents": [
            {
                "role": "author",
                "name": {
                    "given": "B.N. Srinivasarao",
                    "family": "B.N. Srinivasarao"
                },
                "sequence": "first"
            },
            {
                "role": "publisher",
                "name": {
                    "org": "Longman Publishers"
                }
            }
        ],
        "dates": {
            "published": "2022-07-03",
            "date_type": "PublicationDate",
            "online": "2022-07-03"
        },
        "language": "en",
        "container": {
            "type": "Journal",
            "titles": [
                {
                    "value": "Journal of Science & Technology",
                    "type": "PrincipalTitle"
                }
            ],
            "identifiers": [
                {
                    "type": "ISSN",
                    "value": "2456-5660",
                    "medium": "electronic"
                }
            ],
            "volume": "7",
            "issue": "2",
            "pages": {
                "first": "21",
                "last": "29"
            }
        },
        "links": [
            {
                "url": "https://www.jst.org.in/index.php/pub/article/view/253",
                "return_type": "text/html",
                "primary": true
            },
            {
                "url": "https://www.jst.org.in/index.php/pub/article/download/253/1152",
                "purpose": "text-mining",
                "return_type": "application/pdf"
            },
            {
                "url": "https://www.jst.org.in/index.php/pub/article/download/253/2213",
                "purpose": "text-mining",
                "return_type": "application/xml"
            },
            {
                "url": "https://jst.org.in/admin/uploads/JST070129.pdf",
                "purpose": "similarity-checking"
            }
        ],
        "abstract": {
            "value": "Static RAM architecture is an important part in the digital data processing devices like DSP’s Micro Processors and Embedded systems for general purpose or specific purpose applications. Demand of manufacturing compact devices are increasing day by day, to make the compact devices the design of internal circuits area also should be reduced. This will in turn reduces the overall size of the device. In this paper two 128 bytes SRAM architectures are implemented with conventional six transistors SRAM cell and single ended three transistor SRAM cell from the scratch to layout level. The designs are compared in terms of power consumption, area, and speed with 45nm technology. The implemented design area is reduced by 57.14% with 92.37% reduced power consumption and with 89.98% improved performance.",
            "lang": "en"
        },
        "license": {
            "url": "https://creativecommons.org/licenses/by/4.0",
            "start": "2022-07-03",
            "applies_to": "vor"
        },
        "references": [
            {
                "key": "ref1",
                "doi": "10.1109/les.2017.2750140",
                "unstructured": "Samira Ataei and James E “A 64 kB Approximate SRAM Architecture for Low-Power Video Applications,” IEEE Embedded Systems Letters 2017"
            },
            {
                "key": "ref2",
                "unstructured": "B.N. Srinivasa Rao, Ch. Jhansi “Design And Analysis of SRAM Array Architectures”, International Journal of Management, Technology And Engineering, Volume 9, Issue 1, January 2019"
            },
            {
                "key": "ref3",
                "doi": "10.1109/tcsvt.2011.2105550",
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            {
                "key": "ref4",
                "doi": "10.1109/tvlsi.2009.2031468",
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            },
            {
                "key": "ref5",
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            },
            {
                "key": "ref6",
                "doi": "10.1109/tvlsi.2015.2450500",
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            },
            {
                "key": "ref7",
                "doi": "10.1109/tvlsi.2014.2377518",
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            },
            {
                "key": "ref8",
                "doi": "10.1109/jssc.2008.2011972",
                "unstructured": "Ik Joon Chang, Jae-Joon Kim, Sang Phill Park and Kaushik Roy (2009), ‘A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS’, IEEE Journal of Solid-state Circuits, Vol. 44, No. 2"
            },
            {
                "key": "ref9",
                "doi": "10.35940/ijrte.d4264.118419",
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            },
            {
                "key": "ref10",
                "doi": "10.36227/techrxiv.173687647.77078261/v1",
                "unstructured": "G. Torrens (Member, IEEE), B. Alorda (Member, IEEE), C. Carmona, D. Malagón-Periánez, J. Segura (Member,IEEE), S.A. Bota (Senior Member, IEEE) “A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors”, IEEE Transactions on Emerging Topics in Computing, 2017"
            }
        ],
        "record": {
            "registrant": "Longman Publishers",
            "registered": "2024-02-16",
            "updated": "2026-09-17",
            "issue_number": 1,
            "source": "crossref-api",
            "source_agency": "Crossref (member 25296)"
        }
    },
    "record_sha256": "424548e5d8e5be3d53db4cfc4abd2716d1d6a6f6cc12e211bcb50dadec7e8035",
    "handle": {
        "synced_at": "2026-10-01 18:12:35",
        "url": "https://www.jst.org.in/index.php/pub/article/view/253"
    },
    "links": {
        "record_page": "https://registry.smartscholars.in/record.php?doi=10.46243%2Fjst.2022.v7.i02.pp21-29",
        "system_metadata": "https://registry.smartscholars.in/resolve.php?doi=10.46243%2Fjst.2022.v7.i02.pp21-29&as=system",
        "history": "https://registry.smartscholars.in/api.php?action=history&doi=10.46243%2Fjst.2022.v7.i02.pp21-29",
        "kernel_xml": "https://registry.smartscholars.in/resolve.php?doi=10.46243%2Fjst.2022.v7.i02.pp21-29&as=xml"
    }
}