Cite this DOI

C.Arunabala (2018). Diagnosis of Logic and Memory Resources in FPGAs Using Embedded Processor Based Built-In Self-Test. *Journal of Science & Technology*, *03*(02), 47–56. https://doi.org/10.46243/jstj.2018.v3.i2.178

@article{carunabala2018diagnosis,
  author    = {C.Arunabala},
  title     = {{Diagnosis of Logic and Memory Resources in FPGAs Using Embedded Processor Based Built-In Self-Test}},
  journal   = {Journal of Science \& Technology},
  year      = {2018},
  month     = {mar},
  volume    = {03},
  number    = {02},
  pages     = {47--56},
  publisher = {Longman Publishers},
  issn      = {2456-5660},
  doi       = {10.46243/jstj.2018.v3.i2.178},
  url       = {https://doi.org/10.46243/jstj.2018.v3.i2.178},
  language  = {en},
  abstract  = {We present an embedded processor based approach for Built-In Self-Test (BIST) and diagnosis of pro-grammable logic and memory resources in Field Programmable Gate Arrays (FPGAs). The resources under test include the programmable logic blocks (PLBs), large random access memories (RAMs), and digital signal proces-sors (DSPs) in all of their modes of operation. The approach is applicable to any FPGA that supports dynamic par-tial reconfiguration via an embedded processor core. As a case study, we present the application to test and diag-nose logic and memory resources in the Xilinx Virtex-4 series FPGA. We also exploit architectural features to en-hance dynamic partial reconfiguration for BIST to reduce the amount of program memory storage for the embedded processor core as well as the total time required for BIST}
}

TY  - JOUR
TI  - Diagnosis of Logic and Memory Resources in FPGAs Using Embedded Processor Based Built-In Self-Test
AU  - C.Arunabala
JO  - Journal of Science & Technology
PY  - 2018
DA  - 2018/03/01/
VL  - 03
IS  - 02
SP  - 47
EP  - 56
PB  - Longman Publishers
SN  - 2456-5660
LA  - en
AB  - We present an embedded processor based approach for Built-In Self-Test (BIST) and diagnosis of pro-grammable logic and memory resources in Field Programmable Gate Arrays (FPGAs). The resources under test include the programmable logic blocks (PLBs), large random access memories (RAMs), and digital signal proces-sors (DSPs) in all of their modes of operation. The approach is applicable to any FPGA that supports dynamic par-tial reconfiguration via an embedded processor core. As a case study, we present the application to test and diag-nose logic and memory resources in the Xilinx Virtex-4 series FPGA. We also exploit architectural features to en-hance dynamic partial reconfiguration for BIST to reduce the amount of program memory storage for the embedded processor core as well as the total time required for BIST
DO  - 10.46243/jstj.2018.v3.i2.178
UR  - https://doi.org/10.46243/jstj.2018.v3.i2.178
ER  -

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    "id": "10.46243/jstj.2018.v3.i2.178",
    "DOI": "10.46243/jstj.2018.v3.i2.178",
    "URL": "https://doi.org/10.46243/jstj.2018.v3.i2.178",
    "title": "Diagnosis of Logic and Memory Resources in FPGAs Using Embedded Processor Based Built-In Self-Test",
    "source": "Smart Scholars DOI Registry",
    "container-title": "Journal of Science & Technology",
    "author": [
        {
            "family": "C.Arunabala"
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                2018,
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    "volume": "03",
    "issue": "02",
    "page": "47-56",
    "publisher": "Longman Publishers",
    "language": "en",
    "abstract": "We present an embedded processor based approach for Built-In Self-Test (BIST) and diagnosis of pro-grammable logic and memory resources in Field Programmable Gate Arrays (FPGAs). The resources under test include the programmable logic blocks (PLBs), large random access memories (RAMs), and digital signal proces-sors (DSPs) in all of their modes of operation. The approach is applicable to any FPGA that supports dynamic par-tial reconfiguration via an embedded processor core. As a case study, we present the application to test and diag-nose logic and memory resources in the Xilinx Virtex-4 series FPGA. We also exploit architectural features to en-hance dynamic partial reconfiguration for BIST to reduce the amount of program memory storage for the embedded processor core as well as the total time required for BIST",
    "ISSN": "2456-5660"
}

From the record as registered (version 2) — the record and its history. Programs: https://registry.smartscholars.in/api.php?action=cite&doi=10.46243%2Fjstj.2018.v3.i2.178 gives all four in one JSON answer.