Cite this DOI

N. Dandare, M. S., & H. Deshmukh, M. A. (2018). Design of DPLL Using Sub-Micron 45 nm CMOS Technology and Implementation Using Microwind 3.1 Software. *Journal of Science & Technology*, *03*(01), 22–32. https://doi.org/10.46243/jstj.2018.v3.i1.163

@article{ndandare2018design,
  author    = {N. Dandare, Mr. Shankar and H. Deshmukh, Ms. Ankita},
  title     = {{Design of DPLL Using Sub-Micron 45 nm CMOS Technology and Implementation Using Microwind 3.1 Software}},
  journal   = {Journal of Science \& Technology},
  year      = {2018},
  month     = {jan},
  volume    = {03},
  number    = {01},
  pages     = {22--32},
  publisher = {Longman Publishers},
  issn      = {2456-5660},
  doi       = {10.46243/jstj.2018.v3.i1.163},
  url       = {https://doi.org/10.46243/jstj.2018.v3.i1.163},
  language  = {en},
  abstract  = {Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This paper introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind 3.1 is used to design and simulate an integrated circuit at physical description level. The performance of DPLL is also observed for the different variable input frequencies and result is observed up to the mark. The lock range for the DPLL and lock time is was also observed as expected}
}

TY  - JOUR
TI  - Design of DPLL Using Sub-Micron 45 nm CMOS Technology and Implementation Using Microwind 3.1 Software
AU  - N. Dandare, Mr. Shankar
AU  - H. Deshmukh, Ms. Ankita
JO  - Journal of Science & Technology
PY  - 2018
DA  - 2018/01/04/
VL  - 03
IS  - 01
SP  - 22
EP  - 32
PB  - Longman Publishers
SN  - 2456-5660
LA  - en
AB  - Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This paper introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind 3.1 is used to design and simulate an integrated circuit at physical description level. The performance of DPLL is also observed for the different variable input frequencies and result is observed up to the mark. The lock range for the DPLL and lock time is was also observed as expected
DO  - 10.46243/jstj.2018.v3.i1.163
UR  - https://doi.org/10.46243/jstj.2018.v3.i1.163
ER  -

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    "type": "article-journal",
    "id": "10.46243/jstj.2018.v3.i1.163",
    "DOI": "10.46243/jstj.2018.v3.i1.163",
    "URL": "https://doi.org/10.46243/jstj.2018.v3.i1.163",
    "title": "Design of DPLL Using Sub-Micron 45 nm CMOS Technology and Implementation Using Microwind 3.1 Software",
    "source": "Smart Scholars DOI Registry",
    "container-title": "Journal of Science & Technology",
    "author": [
        {
            "family": "N. Dandare",
            "given": "Mr. Shankar"
        },
        {
            "family": "H. Deshmukh",
            "given": "Ms. Ankita"
        }
    ],
    "issued": {
        "date-parts": [
            [
                2018,
                1,
                4
            ]
        ]
    },
    "volume": "03",
    "issue": "01",
    "page": "22-32",
    "publisher": "Longman Publishers",
    "language": "en",
    "abstract": "Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This paper introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind 3.1 is used to design and simulate an integrated circuit at physical description level. The performance of DPLL is also observed for the different variable input frequencies and result is observed up to the mark. The lock range for the DPLL and lock time is was also observed as expected",
    "ISSN": "2456-5660"
}

From the record as registered (version 2) — the record and its history. Programs: https://registry.smartscholars.in/api.php?action=cite&doi=10.46243%2Fjstj.2018.v3.i1.163 gives all four in one JSON answer.