Cite this DOI

CHINTHALA KAVYA, C. K. (2023). AN STRATEGY OF POWER AND AREA COMPETENT APPROXIMATE MULTIPLIERS. *Journal of Science & Technology*, *8*(1), 6–18. https://doi.org/10.46243/jst.2023.v8.i01.pp06-18

@article{chinthalakavya2023strategy,
  author    = {CHINTHALA KAVYA, CHINTHALA KAVYA},
  title     = {{AN STRATEGY OF POWER AND AREA COMPETENT APPROXIMATE MULTIPLIERS}},
  journal   = {Journal of Science \& Technology},
  year      = {2023},
  month     = {mar},
  volume    = {8},
  number    = {1},
  pages     = {6--18},
  publisher = {Longman Publishers},
  issn      = {2456-5660},
  doi       = {10.46243/jst.2023.v8.i01.pp06-18},
  url       = {https://doi.org/10.46243/jst.2023.v8.i01.pp06-18},
  language  = {en},
  abstract  = {In this paper, the area of efficiency multiplier put a sign suggests a fixed width through a replica redundancy through adoption My tolerance for noise (ANT) architecture with a multiplier of fixed width to build a redundancy version precision cutting Masa (RPR). ANT proposed architecture can meet the demand for high precision, low power consumption, and region Efficiency. RPR fixed-width design with error compensation through the circles of the possibilities and statistical analysis. use the When a partial product of the correct input vectors and vectors fixed in the palace and put in place to reduce truncation errors, hardware Failure holding circuit can be simplified compensation. The multiplier ANT 16 × 16 bits, the circuit area in our RPR fixed width It may be less, energy consumption in the design of ants can be saved as compared with the ANT state of the art design}
}

TY  - JOUR
TI  - AN STRATEGY OF POWER AND AREA COMPETENT APPROXIMATE MULTIPLIERS
AU  - CHINTHALA KAVYA, CHINTHALA KAVYA
JO  - Journal of Science & Technology
PY  - 2023
DA  - 2023/03/02/
VL  - 8
IS  - 1
SP  - 6
EP  - 18
PB  - Longman Publishers
SN  - 2456-5660
LA  - en
AB  - In this paper, the area of efficiency multiplier put a sign suggests a fixed width through a replica redundancy through adoption My tolerance for noise (ANT) architecture with a multiplier of fixed width to build a redundancy version precision cutting Masa (RPR). ANT proposed architecture can meet the demand for high precision, low power consumption, and region Efficiency. RPR fixed-width design with error compensation through the circles of the possibilities and statistical analysis. use the When a partial product of the correct input vectors and vectors fixed in the palace and put in place to reduce truncation errors, hardware Failure holding circuit can be simplified compensation. The multiplier ANT 16 × 16 bits, the circuit area in our RPR fixed width It may be less, energy consumption in the design of ants can be saved as compared with the ANT state of the art design
DO  - 10.46243/jst.2023.v8.i01.pp06-18
UR  - https://doi.org/10.46243/jst.2023.v8.i01.pp06-18
ER  -

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    "type": "article-journal",
    "id": "10.46243/jst.2023.v8.i01.pp06-18",
    "DOI": "10.46243/jst.2023.v8.i01.pp06-18",
    "URL": "https://doi.org/10.46243/jst.2023.v8.i01.pp06-18",
    "title": "AN STRATEGY OF POWER AND AREA COMPETENT APPROXIMATE MULTIPLIERS",
    "source": "Smart Scholars DOI Registry",
    "container-title": "Journal of Science & Technology",
    "author": [
        {
            "family": "CHINTHALA KAVYA",
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    "issued": {
        "date-parts": [
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                2023,
                3,
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    "volume": "8",
    "issue": "1",
    "page": "6-18",
    "publisher": "Longman Publishers",
    "language": "en",
    "abstract": "In this paper, the area of efficiency multiplier put a sign suggests a fixed width through a replica redundancy through adoption My tolerance for noise (ANT) architecture with a multiplier of fixed width to build a redundancy version precision cutting Masa (RPR). ANT proposed architecture can meet the demand for high precision, low power consumption, and region Efficiency. RPR fixed-width design with error compensation through the circles of the possibilities and statistical analysis. use the When a partial product of the correct input vectors and vectors fixed in the palace and put in place to reduce truncation errors, hardware Failure holding circuit can be simplified compensation. The multiplier ANT 16 × 16 bits, the circuit area in our RPR fixed width It may be less, energy consumption in the design of ants can be saved as compared with the ANT state of the art design",
    "ISSN": "2456-5660"
}

From the record as registered (version 2) — the record and its history. Programs: https://registry.smartscholars.in/api.php?action=cite&doi=10.46243%2Fjst.2023.v8.i01.pp06-18 gives all four in one JSON answer.