Cite this DOI
10.46243/jst.2021.v6.i3.pp62-66 · Enhancement of Underwater Images Using FPGA
APA (7th edition)
Latha, J., G.Usharani, & Author, C. (2021). Enhancement of Underwater Images Using FPGA. *Journal of Science & Technology*, *06*(03), 62–66. https://doi.org/10.46243/jst.2021.v6.i3.pp62-66
⬇ text Italics are shown as *asterisks* in plain text — the journal or book title and the volume.
BibTeX
@article{latha2021enhancement,
author = {Latha, J.Sneha and G.Usharani and Author, Corresponding},
title = {{Enhancement of Underwater Images Using FPGA}},
journal = {Journal of Science \& Technology},
year = {2021},
month = {may},
volume = {06},
number = {03},
pages = {62--66},
publisher = {Longman Publishers},
issn = {2456-5660},
doi = {10.46243/jst.2021.v6.i3.pp62-66},
url = {https://doi.org/10.46243/jst.2021.v6.i3.pp62-66},
language = {en},
abstract = {Due to low illumination and changing environmental circumstances, underwater photography is difficult. The obtained weak images must be upgraded due to limited light offered by the Automated Underwater Vehicles (AUV). In order to employ AUVs, image enhancing algorithms must be created in hardware. Because of their intrinsic parallelism, Field Programmable Gate Arrays (FPGA) have shown to be a superior solution for image processing approaches. Power law transform, contrast stretching, Histogram Equalization, Histogram Stretching, and Negative transformation are among the spatial domain procedures used to preprocess an underwater picture. A comparison of the above-mentioned picture enhancement technique implemented in FPGA is conducted in this work.}
}RIS (EndNote, Zotero, Mendeley)
TY - JOUR TI - Enhancement of Underwater Images Using FPGA AU - Latha, J.Sneha AU - G.Usharani AU - Author, Corresponding JO - Journal of Science & Technology PY - 2021 DA - 2021/05/23/ VL - 06 IS - 03 SP - 62 EP - 66 PB - Longman Publishers SN - 2456-5660 LA - en AB - Due to low illumination and changing environmental circumstances, underwater photography is difficult. The obtained weak images must be upgraded due to limited light offered by the Automated Underwater Vehicles (AUV). In order to employ AUVs, image enhancing algorithms must be created in hardware. Because of their intrinsic parallelism, Field Programmable Gate Arrays (FPGA) have shown to be a superior solution for image processing approaches. Power law transform, contrast stretching, Histogram Equalization, Histogram Stretching, and Negative transformation are among the spatial domain procedures used to preprocess an underwater picture. A comparison of the above-mentioned picture enhancement technique implemented in FPGA is conducted in this work. DO - 10.46243/jst.2021.v6.i3.pp62-66 UR - https://doi.org/10.46243/jst.2021.v6.i3.pp62-66 ER -
CSL-JSON
{
"type": "article-journal",
"id": "10.46243/jst.2021.v6.i3.pp62-66",
"DOI": "10.46243/jst.2021.v6.i3.pp62-66",
"URL": "https://doi.org/10.46243/jst.2021.v6.i3.pp62-66",
"title": "Enhancement of Underwater Images Using FPGA",
"source": "Smart Scholars DOI Registry",
"container-title": "Journal of Science & Technology",
"author": [
{
"family": "Latha",
"given": "J.Sneha"
},
{
"family": "G.Usharani"
},
{
"family": "Author",
"given": "Corresponding"
}
],
"issued": {
"date-parts": [
[
2021,
5,
23
]
]
},
"volume": "06",
"issue": "03",
"page": "62-66",
"publisher": "Longman Publishers",
"language": "en",
"abstract": "Due to low illumination and changing environmental circumstances, underwater photography is difficult. The obtained weak images must be upgraded due to limited light offered by the Automated Underwater Vehicles (AUV). In order to employ AUVs, image enhancing algorithms must be created in hardware. Because of their intrinsic parallelism, Field Programmable Gate Arrays (FPGA) have shown to be a superior solution for image processing approaches. Power law transform, contrast stretching, Histogram Equalization, Histogram Stretching, and Negative transformation are among the spatial domain procedures used to preprocess an underwater picture. A comparison of the above-mentioned picture enhancement technique implemented in FPGA is conducted in this work.",
"ISSN": "2456-5660"
} ⬇ .json What citeproc and reference managers read; the DOI system hands it out for Accept: application/vnd.citationstyles.csl+json, and so does this registry's resolver.
From the record as registered (version 2) — the record and its history. Programs: https://registry.smartscholars.in/api.php?action=cite&doi=10.46243%2Fjst.2021.v6.i3.pp62-66 gives all four in one JSON answer.
