Cite this DOI
10.46243/jst.2021.v6.i01.pp185-194 · TWO-STEP TDC CMOS RESOLUTION WITH BUILT-IN COARSE GAIN CALIBRATION BY PULSE-SHRINKING FINE STAGE
APA (7th edition)
Dr.RANGANAHAN, KRISHNA REDDY, D., SUBRAMANIAN, D., PRAKASH, G., ESWARAIAH, K., & ADAIKALAKUMAR, D. (2021). TWO-STEP TDC CMOS RESOLUTION WITH BUILT-IN COARSE GAIN CALIBRATION BY PULSE-SHRINKING FINE STAGE. *Journal of Science & Technology*, *06*(01), 185–194. https://doi.org/10.46243/jst.2021.v6.i01.pp185-194
⬇ text Italics are shown as *asterisks* in plain text — the journal or book title and the volume.
BibTeX
@article{drranganahan2021twostep,
author = {Dr.RANGANAHAN and KRISHNA REDDY, Dr.EDARA and SUBRAMANIAN, Dr.SHIVA and PRAKASH, G and ESWARAIAH, K and ADAIKALAKUMAR, Dr.P},
title = {{TWO-STEP TDC CMOS RESOLUTION WITH BUILT-IN COARSE GAIN CALIBRATION BY PULSE-SHRINKING FINE STAGE}},
journal = {Journal of Science \& Technology},
year = {2021},
month = {jan},
volume = {06},
number = {01},
pages = {185--194},
publisher = {Longman Publishers},
issn = {2456-5660},
doi = {10.46243/jst.2021.v6.i01.pp185-194},
url = {https://doi.org/10.46243/jst.2021.v6.i01.pp185-194},
language = {en},
abstract = {This article proposes a computerized converter (TDC) solution that can meet a broad range of knowledge and fine-time goals at the same time. The proposed TDC utilizes a beat contracting (PS) plot for a precise target and two-advance (TS) engineering for a larger range in the second phase. The suggested PS TDC solves the undesired non-uniform contracting rate issue that plagues conventional PS TDCs by using an assumed counterbalance beat and a balance beat width detecting method. Due to sign spread and extension fraud between coarse and fine phases, the proposed TS architecture achieves nonlinearity with a few methods, resulting in an inferred coarse increase adjustment mechanism. The replication findings in a 0.18-m normal CMOS innovation show 2.0-ps targetsand 16-piece go connected to 130-ns input time interim of 0.08-mm2 area in a TDC modification. With an 18.0 maws 1.8-V supply, it has a single-shot accuracy of 1.44 ps and operates at 3.3 MS/s.}
}RIS (EndNote, Zotero, Mendeley)
TY - JOUR TI - TWO-STEP TDC CMOS RESOLUTION WITH BUILT-IN COARSE GAIN CALIBRATION BY PULSE-SHRINKING FINE STAGE AU - Dr.RANGANAHAN AU - KRISHNA REDDY, Dr.EDARA AU - SUBRAMANIAN, Dr.SHIVA AU - PRAKASH, G AU - ESWARAIAH, K AU - ADAIKALAKUMAR, Dr.P JO - Journal of Science & Technology PY - 2021 DA - 2021/01/03/ VL - 06 IS - 01 SP - 185 EP - 194 PB - Longman Publishers SN - 2456-5660 LA - en AB - This article proposes a computerized converter (TDC) solution that can meet a broad range of knowledge and fine-time goals at the same time. The proposed TDC utilizes a beat contracting (PS) plot for a precise target and two-advance (TS) engineering for a larger range in the second phase. The suggested PS TDC solves the undesired non-uniform contracting rate issue that plagues conventional PS TDCs by using an assumed counterbalance beat and a balance beat width detecting method. Due to sign spread and extension fraud between coarse and fine phases, the proposed TS architecture achieves nonlinearity with a few methods, resulting in an inferred coarse increase adjustment mechanism. The replication findings in a 0.18-m normal CMOS innovation show 2.0-ps targetsand 16-piece go connected to 130-ns input time interim of 0.08-mm2 area in a TDC modification. With an 18.0 maws 1.8-V supply, it has a single-shot accuracy of 1.44 ps and operates at 3.3 MS/s. DO - 10.46243/jst.2021.v6.i01.pp185-194 UR - https://doi.org/10.46243/jst.2021.v6.i01.pp185-194 ER -
CSL-JSON
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} ⬇ .json What citeproc and reference managers read; the DOI system hands it out for Accept: application/vnd.citationstyles.csl+json, and so does this registry's resolver.
From the record as registered (version 2) — the record and its history. Programs: https://registry.smartscholars.in/api.php?action=cite&doi=10.46243%2Fjst.2021.v6.i01.pp185-194 gives all four in one JSON answer.
