{ "ok": true, "doi": "10.46243/jstj.2018.v3.i1.163", "events": [ { "seq": 1, "kind": "register", "at": "2026-09-29 22:00:33", "by": "Administrator (admin)", "by_kind": "user", "note": "registered at Crossref; record read from api.crossref.org", "changes": [ { "path": "abstract.lang", "from": null, "to": "en" }, { "path": "abstract.value", "from": null, "to": "Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This paper introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind 3.1 is used to design and simulate an integrated circuit at physical description level. The performance of DPLL is also observed for the different variable input frequencies and result is observed up to the mark. The lock range for the DPLL and lock time is was also observed as expected" }, { "path": "agents.0.name.family", "from": null, "to": "N. Dandare" }, { "path": "agents.0.name.given", "from": null, "to": "Mr. Shankar" }, { "path": "agents.0.role", "from": null, "to": "author" }, { "path": "agents.0.sequence", "from": null, "to": "first" }, { "path": "agents.1.name.family", "from": null, "to": "H. Deshmukh" }, { "path": "agents.1.name.given", "from": null, "to": "Ms. Ankita" }, { "path": "agents.1.role", "from": null, "to": "author" }, { "path": "agents.1.sequence", "from": null, "to": "additional" }, { "path": "agents.2.name.org", "from": null, "to": "Longman Publishers" }, { "path": "agents.2.role", "from": null, "to": "publisher" }, { "path": "characters.0", "from": null, "to": "Language" }, { "path": "container.identifiers.0.medium", "from": null, "to": "electronic" }, { "path": "container.identifiers.0.type", "from": null, "to": "ISSN" }, { "path": "container.identifiers.0.value", "from": null, "to": "2456-5660" }, { "path": "container.issue", "from": null, "to": "01" }, { "path": "container.pages.first", "from": null, "to": "22" }, { "path": "container.pages.last", "from": null, "to": "32" }, { "path": "container.titles.0.type", "from": null, "to": "PrincipalTitle" }, { "path": "container.titles.0.value", "from": null, "to": "Journal of Science & Technology" }, { "path": "container.type", "from": null, "to": "Journal" }, { "path": "container.volume", "from": null, "to": "03" }, { "path": "dates.date_type", "from": null, "to": "PublicationDate" }, { "path": "dates.online", "from": null, "to": "2018-01-04" }, { "path": "dates.published", "from": null, "to": "2018-01-04" }, { "path": "doi", "from": null, "to": "10.46243/jstj.2018.v3.i1.163" }, { "path": "format", "from": null, "to": "smartscholars-doi-metadata/1.0" }, { "path": "identifiers.0.type", "from": null, "to": "DOI" }, { "path": "identifiers.0.value", "from": null, "to": "10.46243/jstj.2018.v3.i1.163" }, { "path": "language", "from": null, "to": "en" }, { "path": "license.applies_to", "from": null, "to": "vor" }, { "path": "license.start", "from": null, "to": "2018-01-04" }, { "path": "license.url", "from": null, "to": "https://creativecommons.org/licenses/by/4.0/" }, { "path": "links.0.primary", "from": null, "to": true }, { "path": "links.0.return_type", "from": null, "to": "text/html" }, { "path": "links.0.url", "from": null, "to": "https://www.jst.org.in/index.php/pub/article/view/163" }, { "path": "links.1.purpose", "from": null, "to": "text-mining" }, { "path": "links.1.return_type", "from": null, "to": "application/pdf" }, { "path": "links.1.url", "from": null, "to": "https://www.jst.org.in/index.php/pub/article/download/163/142" }, { "path": "links.2.purpose", "from": null, "to": "text-mining" }, { "path": "links.2.return_type", "from": null, "to": "application/xml" }, { "path": "links.2.url", "from": null, "to": "https://www.jst.org.in/index.php/pub/article/download/163/3428" }, { "path": "links.3.purpose", "from": null, "to": "similarity-checking" }, { "path": "links.3.url", "from": null, "to": "https://www.jst.org.in/index.php/pub/article/view/163/142" }, { "path": "modes.0", "from": null, "to": "Visual" }, { "path": "record.issue_number", "from": null, "to": 1 }, { "path": "record.registered", "from": null, "to": "2026-09-07" }, { "path": "record.registrant", "from": null, "to": "Longman Publishers" }, { "path": "record.source", "from": null, "to": "crossref-api" }, { "path": "record.source_agency", "from": null, "to": "Crossref (member 25296)" }, { "path": "record.updated", "from": null, "to": "2026-09-20" }, { "path": "references.0.key", "from": null, "to": "ref1" }, { "path": "references.0.unstructured", "from": null, "to": "B. Razavi, “Design of Analog CMOS Integrated Circuits,” Tata McGraw Hill Edition,2001" }, { "path": "references.1.key", "from": null, "to": "ref2" }, { "path": "references.1.unstructured", "from": null, "to": "R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation” IEEE Press Series on Microelectronic Systems, Stuart K. Tewksbury and Joe E. Brewer, A John Wiley & Sons, Inc.,Publication,Series Editors 3rd Edition-1964" }, { "path": "references.10.doi", "from": null, "to": "10.1109/primeasia.2015.7450462" }, { "path": "references.10.key", "from": null, "to": "ref11" }, { "path": "references.10.unstructured", "from": null, "to": "Purushothama Chary P et al., \"1.2 mW 2.4 GHz PLL for ZigBee and BLE standard in single-well 0.18 µm CMOS with efficient divider architecture,\" IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Hyderabad, 2015, pp. 17-20" }, { "path": "references.11.doi", "from": null, "to": "10.1109/wocn.2016.7759029" }, { "path": "references.11.key", "from": null, "to": "ref12" }, { "path": "references.11.unstructured", "from": null, "to": "G. Bhargav, G. Prasad, S. Datta Canchi and B. Chanikya, \"Design and analysis of phase locked loop in 90nm CMOS,\" Thirteenth International Conference on Wireless &Optical Authors ProfileCommunications Networks (WOCN), Hyderabad, 2016, pp1-7" }, { "path": "references.12.doi", "from": null, "to": "10.1109/jssc.2010.2042250" }, { "path": "references.12.key", "from": null, "to": "ref13" }, { "path": "references.12.unstructured", "from": null, "to": "Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, Senior Member, IEEE ”A Phase Selecting Digital Phase Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010" }, { "path": "references.13.doi", "from": null, "to": "10.1109/rfic.2011.5940678" }, { "path": "references.13.key", "from": null, "to": "ref14" }, { "path": "references.13.unstructured", "from": null, "to": "W. S. Titus and J. G. Kenney, \"A 5.6GHz to 11.5GHz DCO for digital dual loop CDRs,\" 2011 IEEE Radio Frequency Integrated Circuits Symposium, Baltimore, MD, 2011, pp. 14" }, { "path": "references.14.doi", "from": null, "to": "10.5121/acij.2011.2605" }, { "path": "references.14.key", "from": null, "to": "ref15" }, { "path": "references.14.unstructured", "from": null, "to": "Delvadiya Harikrushna, Mukesh Tiwari, Jay Karan Singh,Anubhuti Khare, “Design and Implementation of DPLL with Phase Frequency Detector Using 45nm CMOS Technology”,International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 1, Issue 2" }, { "path": "references.15.doi", "from": null, "to": "10.1109/eeei.2010.5662107" }, { "path": "references.15.key", "from": null, "to": "ref16" }, { "path": "references.15.unstructured", "from": null, "to": "Arkadiy Morgenshtein, Idan Shwartz,Alexander Fish, “Gate Diffusion Input(GDI) Logic in Standard CMOS Nanoscale Process”, 26th convention of Electrical and Electronics Engineers, Israel,IEEE 2010" }, { "path": "references.16.doi", "from": null, "to": "10.1109/cicn.2011.37" }, { "path": "references.16.key", "from": null, "to": "ref17" }, { "path": "references.16.unstructured", "from": null, "to": "Atul Kumar Nishad and Rajeevan Chandel, “Analysis of Low Power High Performance XOR Gate using GDI Technique”,Conference, IEEE 2011 BIBLIOGRAPHY OF AUTHORS" }, { "path": "references.2.doi", "from": null, "to": "10.1109/jssc.2010.2042250" }, { "path": "references.2.key", "from": null, "to": "ref3" }, { "path": "references.2.unstructured", "from": null, "to": "Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, Senior Member, IEEE ”A Phase Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology” IEEE Journal Of Solid-State Circuits, Vol. 45, No. 4, April 2010" }, { "path": "references.3.key", "from": null, "to": "ref4" }, { "path": "references.3.unstructured", "from": null, "to": "R. E. Best, “Phase locked loops design, simulation and application”, Mc Graw Hill 2003" }, { "path": "references.4.key", "from": null, "to": "ref5" }, { "path": "references.4.unstructured", "from": null, "to": "E. Sicard, Syed Mahfuzul Aziz, “Introducing 45 nm technology in Microwind3,” Microwind application note" }, { "path": "references.5.doi", "from": null, "to": "10.1109/spin52536.2021.9566035" }, { "path": "references.5.key", "from": null, "to": "ref6" }, { "path": "references.5.unstructured", "from": null, "to": "Rupesh Kumar Patlani, Rekha Yadav, “Design of Low Power Ring VCO and LC-VCO using 45 nm Technology ”,IJISET, Vol. 1, Issue 4, June 2014" }, { "path": "references.6.doi", "from": null, "to": "10.5220/0005547302670272" }, { "path": "references.6.key", "from": null, "to": "ref7" }, { "path": "references.6.unstructured", "from": null, "to": "F. Hajilou, E. Mazidi and S. Ardalan, \"DPA resistanceenhancement through a self-healing PLL based power mask,\"2015 12th International Joint Conference on e-Business and Telecommunications (ICETE), Colmar, 2015, pp. 267-272" }, { "path": "references.7.doi", "from": null, "to": "10.1109/dcas.2016.7791144" }, { "path": "references.7.key", "from": null, "to": "ref8" }, { "path": "references.7.unstructured", "from": null, "to": "F. Lei and M. H. White, \"A study of the low frequency noise (LFN) in reference injected Phase Locked Loops (PLL-RI),\" 2016 IEEE Dallas Circuits and Systems Conference(DCAS), Arligton, TX, 2016, pp. 1-4" }, { "path": "references.8.doi", "from": null, "to": "10.1109/iccicct.2015.7475300" }, { "path": "references.8.key", "from": null, "to": "ref9" }, { "path": "references.8.unstructured", "from": null, "to": "V. Muddi, K. D. Shinde and Shivaprasad B K, \"Design and implementation of 1 GHz Current Starved Voltage Controlled Oscillator (VCO) for PLL using 90nm CMOS technology,\" 2015 International Conference on Control Instrumentation, Communication and ComputationaTechnologies (ICCICCT), Kumaracoil, 2015, pp. 335-339. [10]V. Nagarajan and B. Raju, \"Charge pump boost converter with PLL using compensator technique,\" 2016 International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, 2016, pp. 2327-2331" }, { "path": "references.9.doi", "from": null, "to": "10.1109/iceeot.2016.7755307" }, { "path": "references.9.key", "from": null, "to": "ref10" }, { "path": "references.9.unstructured", "from": null, "to": "B. Goyal, S. Suman and P. K. Ghosh, \"Design of charge pump PLL using improved performance ring VCO,\" 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai, 2016, pp. 3254-3258" }, { "path": "referent", "from": null, "to": "Creation" }, { "path": "structural_type", "from": null, "to": "Digital" }, { "path": "titles.0.lang", "from": null, "to": "en" }, { "path": "titles.0.type", "from": null, "to": "PrincipalTitle" }, { "path": "titles.0.value", "from": null, "to": "Design of DPLL Using Sub-Micron 45 nm CMOS Technology and Implementation Using Microwind 3.1 Software" }, { "path": "type", "from": null, "to": "JournalArticle" } ], "record_after": { "format": "smartscholars-doi-metadata/1.0", "doi": "10.46243/jstj.2018.v3.i1.163", "referent": "Creation", "type": "JournalArticle", "structural_type": "Digital", "modes": [ "Visual" ], "characters": [ "Language" ], "titles": [ { "value": "Design of DPLL Using Sub-Micron 45 nm CMOS Technology and Implementation Using Microwind 3.1 Software", "type": "PrincipalTitle", "lang": "en" } ], "identifiers": [ { "type": "DOI", "value": "10.46243/jstj.2018.v3.i1.163" } ], "agents": [ { "role": "author", "name": { "given": "Mr. Shankar", "family": "N. Dandare" }, "sequence": "first" }, { "role": "author", "name": { "given": "Ms. Ankita", "family": "H. Deshmukh" }, "sequence": "additional" }, { "role": "publisher", "name": { "org": "Longman Publishers" } } ], "dates": { "published": "2018-01-04", "date_type": "PublicationDate", "online": "2018-01-04" }, "language": "en", "container": { "type": "Journal", "titles": [ { "value": "Journal of Science & Technology", "type": "PrincipalTitle" } ], "identifiers": [ { "type": "ISSN", "value": "2456-5660", "medium": "electronic" } ], "volume": "03", "issue": "01", "pages": { "first": "22", "last": "32" } }, "links": [ { "url": "https://www.jst.org.in/index.php/pub/article/view/163", "return_type": "text/html", "primary": true }, { "url": "https://www.jst.org.in/index.php/pub/article/download/163/142", "purpose": "text-mining", "return_type": "application/pdf" }, { "url": "https://www.jst.org.in/index.php/pub/article/download/163/3428", "purpose": "text-mining", "return_type": "application/xml" }, { "url": "https://www.jst.org.in/index.php/pub/article/view/163/142", "purpose": "similarity-checking" } ], "abstract": { "value": "Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This paper introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind 3.1 is used to design and simulate an integrated circuit at physical description level. The performance of DPLL is also observed for the different variable input frequencies and result is observed up to the mark. The lock range for the DPLL and lock time is was also observed as expected", "lang": "en" }, "license": { "url": "https://creativecommons.org/licenses/by/4.0/", "start": "2018-01-04", "applies_to": "vor" }, "references": [ { "key": "ref1", "unstructured": "B. Razavi, “Design of Analog CMOS Integrated Circuits,” Tata McGraw Hill Edition,2001" }, { "key": "ref2", "unstructured": "R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation” IEEE Press Series on Microelectronic Systems, Stuart K. Tewksbury and Joe E. Brewer, A John Wiley & Sons, Inc.,Publication,Series Editors 3rd Edition-1964" }, { "key": "ref3", "doi": "10.1109/jssc.2010.2042250", "unstructured": "Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, Senior Member, IEEE ”A Phase Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology” IEEE Journal Of Solid-State Circuits, Vol. 45, No. 4, April 2010" }, { "key": "ref4", "unstructured": "R. E. Best, “Phase locked loops design, simulation and application”, Mc Graw Hill 2003" }, { "key": "ref5", "unstructured": "E. Sicard, Syed Mahfuzul Aziz, “Introducing 45 nm technology in Microwind3,” Microwind application note" }, { "key": "ref6", "doi": "10.1109/spin52536.2021.9566035", "unstructured": "Rupesh Kumar Patlani, Rekha Yadav, “Design of Low Power Ring VCO and LC-VCO using 45 nm Technology ”,IJISET, Vol. 1, Issue 4, June 2014" }, { "key": "ref7", "doi": "10.5220/0005547302670272", "unstructured": "F. Hajilou, E. Mazidi and S. Ardalan, \"DPA resistanceenhancement through a self-healing PLL based power mask,\"2015 12th International Joint Conference on e-Business and Telecommunications (ICETE), Colmar, 2015, pp. 267-272" }, { "key": "ref8", "doi": "10.1109/dcas.2016.7791144", "unstructured": "F. Lei and M. H. White, \"A study of the low frequency noise (LFN) in reference injected Phase Locked Loops (PLL-RI),\" 2016 IEEE Dallas Circuits and Systems Conference(DCAS), Arligton, TX, 2016, pp. 1-4" }, { "key": "ref9", "doi": "10.1109/iccicct.2015.7475300", "unstructured": "V. Muddi, K. D. Shinde and Shivaprasad B K, \"Design and implementation of 1 GHz Current Starved Voltage Controlled Oscillator (VCO) for PLL using 90nm CMOS technology,\" 2015 International Conference on Control Instrumentation, Communication and ComputationaTechnologies (ICCICCT), Kumaracoil, 2015, pp. 335-339. [10]V. Nagarajan and B. Raju, \"Charge pump boost converter with PLL using compensator technique,\" 2016 International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, 2016, pp. 2327-2331" }, { "key": "ref10", "doi": "10.1109/iceeot.2016.7755307", "unstructured": "B. Goyal, S. Suman and P. K. Ghosh, \"Design of charge pump PLL using improved performance ring VCO,\" 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai, 2016, pp. 3254-3258" }, { "key": "ref11", "doi": "10.1109/primeasia.2015.7450462", "unstructured": "Purushothama Chary P et al., \"1.2 mW 2.4 GHz PLL for ZigBee and BLE standard in single-well 0.18 µm CMOS with efficient divider architecture,\" IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Hyderabad, 2015, pp. 17-20" }, { "key": "ref12", "doi": "10.1109/wocn.2016.7759029", "unstructured": "G. Bhargav, G. Prasad, S. Datta Canchi and B. Chanikya, \"Design and analysis of phase locked loop in 90nm CMOS,\" Thirteenth International Conference on Wireless &Optical Authors ProfileCommunications Networks (WOCN), Hyderabad, 2016, pp1-7" }, { "key": "ref13", "doi": "10.1109/jssc.2010.2042250", "unstructured": "Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, Senior Member, IEEE ”A Phase Selecting Digital Phase Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010" }, { "key": "ref14", "doi": "10.1109/rfic.2011.5940678", "unstructured": "W. S. Titus and J. G. Kenney, \"A 5.6GHz to 11.5GHz DCO for digital dual loop CDRs,\" 2011 IEEE Radio Frequency Integrated Circuits Symposium, Baltimore, MD, 2011, pp. 14" }, { "key": "ref15", "doi": "10.5121/acij.2011.2605", "unstructured": "Delvadiya Harikrushna, Mukesh Tiwari, Jay Karan Singh,Anubhuti Khare, “Design and Implementation of DPLL with Phase Frequency Detector Using 45nm CMOS Technology”,International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 1, Issue 2" }, { "key": "ref16", "doi": "10.1109/eeei.2010.5662107", "unstructured": "Arkadiy Morgenshtein, Idan Shwartz,Alexander Fish, “Gate Diffusion Input(GDI) Logic in Standard CMOS Nanoscale Process”, 26th convention of Electrical and Electronics Engineers, Israel,IEEE 2010" }, { "key": "ref17", "doi": "10.1109/cicn.2011.37", "unstructured": "Atul Kumar Nishad and Rajeevan Chandel, “Analysis of Low Power High Performance XOR Gate using GDI Technique”,Conference, IEEE 2011 BIBLIOGRAPHY OF AUTHORS" } ], "record": { "registrant": "Longman Publishers", "registered": "2026-09-07", "updated": "2026-09-20", "issue_number": 1, "source": "crossref-api", "source_agency": "Crossref (member 25296)" } }, "url_after": "https://www.jst.org.in/index.php/pub/article/view/163", "sha256_before": null, "sha256_after": "c3160c644734e1d16386e066c4700ca0d1e2e4e37306a29c8dc7e142bbb84ad5" }, { "seq": 2, "kind": "update", "at": "2026-09-29 23:59:52", "by": "Administrator (admin)", "by_kind": "user", "note": "record re-read from api.crossref.org", "changes": [ { "path": "container.titles.0.value", "from": "Journal of Science & Technology", "to": "Journal of Science & Technology" } ], "record_after": { "format": "smartscholars-doi-metadata/1.0", "doi": "10.46243/jstj.2018.v3.i1.163", "referent": "Creation", "type": "JournalArticle", "structural_type": "Digital", "modes": [ "Visual" ], "characters": [ "Language" ], "titles": [ { "value": "Design of DPLL Using Sub-Micron 45 nm CMOS Technology and Implementation Using Microwind 3.1 Software", "type": "PrincipalTitle", "lang": "en" } ], "identifiers": [ { "type": "DOI", "value": "10.46243/jstj.2018.v3.i1.163" } ], "agents": [ { "role": "author", "name": { "given": "Mr. Shankar", "family": "N. Dandare" }, "sequence": "first" }, { "role": "author", "name": { "given": "Ms. Ankita", "family": "H. Deshmukh" }, "sequence": "additional" }, { "role": "publisher", "name": { "org": "Longman Publishers" } } ], "dates": { "published": "2018-01-04", "date_type": "PublicationDate", "online": "2018-01-04" }, "language": "en", "container": { "type": "Journal", "titles": [ { "value": "Journal of Science & Technology", "type": "PrincipalTitle" } ], "identifiers": [ { "type": "ISSN", "value": "2456-5660", "medium": "electronic" } ], "volume": "03", "issue": "01", "pages": { "first": "22", "last": "32" } }, "links": [ { "url": "https://www.jst.org.in/index.php/pub/article/view/163", "return_type": "text/html", "primary": true }, { "url": "https://www.jst.org.in/index.php/pub/article/download/163/142", "purpose": "text-mining", "return_type": "application/pdf" }, { "url": "https://www.jst.org.in/index.php/pub/article/download/163/3428", "purpose": "text-mining", "return_type": "application/xml" }, { "url": "https://www.jst.org.in/index.php/pub/article/view/163/142", "purpose": "similarity-checking" } ], "abstract": { "value": "Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This paper introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind 3.1 is used to design and simulate an integrated circuit at physical description level. The performance of DPLL is also observed for the different variable input frequencies and result is observed up to the mark. The lock range for the DPLL and lock time is was also observed as expected", "lang": "en" }, "license": { "url": "https://creativecommons.org/licenses/by/4.0/", "start": "2018-01-04", "applies_to": "vor" }, "references": [ { "key": "ref1", "unstructured": "B. Razavi, “Design of Analog CMOS Integrated Circuits,” Tata McGraw Hill Edition,2001" }, { "key": "ref2", "unstructured": "R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation” IEEE Press Series on Microelectronic Systems, Stuart K. Tewksbury and Joe E. Brewer, A John Wiley & Sons, Inc.,Publication,Series Editors 3rd Edition-1964" }, { "key": "ref3", "doi": "10.1109/jssc.2010.2042250", "unstructured": "Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, Senior Member, IEEE ”A Phase Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology” IEEE Journal Of Solid-State Circuits, Vol. 45, No. 4, April 2010" }, { "key": "ref4", "unstructured": "R. E. Best, “Phase locked loops design, simulation and application”, Mc Graw Hill 2003" }, { "key": "ref5", "unstructured": "E. Sicard, Syed Mahfuzul Aziz, “Introducing 45 nm technology in Microwind3,” Microwind application note" }, { "key": "ref6", "doi": "10.1109/spin52536.2021.9566035", "unstructured": "Rupesh Kumar Patlani, Rekha Yadav, “Design of Low Power Ring VCO and LC-VCO using 45 nm Technology ”,IJISET, Vol. 1, Issue 4, June 2014" }, { "key": "ref7", "doi": "10.5220/0005547302670272", "unstructured": "F. Hajilou, E. Mazidi and S. Ardalan, \"DPA resistanceenhancement through a self-healing PLL based power mask,\"2015 12th International Joint Conference on e-Business and Telecommunications (ICETE), Colmar, 2015, pp. 267-272" }, { "key": "ref8", "doi": "10.1109/dcas.2016.7791144", "unstructured": "F. Lei and M. H. White, \"A study of the low frequency noise (LFN) in reference injected Phase Locked Loops (PLL-RI),\" 2016 IEEE Dallas Circuits and Systems Conference(DCAS), Arligton, TX, 2016, pp. 1-4" }, { "key": "ref9", "doi": "10.1109/iccicct.2015.7475300", "unstructured": "V. Muddi, K. D. Shinde and Shivaprasad B K, \"Design and implementation of 1 GHz Current Starved Voltage Controlled Oscillator (VCO) for PLL using 90nm CMOS technology,\" 2015 International Conference on Control Instrumentation, Communication and ComputationaTechnologies (ICCICCT), Kumaracoil, 2015, pp. 335-339. [10]V. Nagarajan and B. Raju, \"Charge pump boost converter with PLL using compensator technique,\" 2016 International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, 2016, pp. 2327-2331" }, { "key": "ref10", "doi": "10.1109/iceeot.2016.7755307", "unstructured": "B. Goyal, S. Suman and P. K. Ghosh, \"Design of charge pump PLL using improved performance ring VCO,\" 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai, 2016, pp. 3254-3258" }, { "key": "ref11", "doi": "10.1109/primeasia.2015.7450462", "unstructured": "Purushothama Chary P et al., \"1.2 mW 2.4 GHz PLL for ZigBee and BLE standard in single-well 0.18 µm CMOS with efficient divider architecture,\" IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Hyderabad, 2015, pp. 17-20" }, { "key": "ref12", "doi": "10.1109/wocn.2016.7759029", "unstructured": "G. Bhargav, G. Prasad, S. Datta Canchi and B. Chanikya, \"Design and analysis of phase locked loop in 90nm CMOS,\" Thirteenth International Conference on Wireless &Optical Authors ProfileCommunications Networks (WOCN), Hyderabad, 2016, pp1-7" }, { "key": "ref13", "doi": "10.1109/jssc.2010.2042250", "unstructured": "Ping-Hsuan Hsieh, Jay Maxey, and Chih-Kong Ken Yang, Senior Member, IEEE ”A Phase Selecting Digital Phase Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010" }, { "key": "ref14", "doi": "10.1109/rfic.2011.5940678", "unstructured": "W. S. Titus and J. G. Kenney, \"A 5.6GHz to 11.5GHz DCO for digital dual loop CDRs,\" 2011 IEEE Radio Frequency Integrated Circuits Symposium, Baltimore, MD, 2011, pp. 14" }, { "key": "ref15", "doi": "10.5121/acij.2011.2605", "unstructured": "Delvadiya Harikrushna, Mukesh Tiwari, Jay Karan Singh,Anubhuti Khare, “Design and Implementation of DPLL with Phase Frequency Detector Using 45nm CMOS Technology”,International Journal of Computer Technology and Electronics Engineering (IJCTEE) Volume 1, Issue 2" }, { "key": "ref16", "doi": "10.1109/eeei.2010.5662107", "unstructured": "Arkadiy Morgenshtein, Idan Shwartz,Alexander Fish, “Gate Diffusion Input(GDI) Logic in Standard CMOS Nanoscale Process”, 26th convention of Electrical and Electronics Engineers, Israel,IEEE 2010" }, { "key": "ref17", "doi": "10.1109/cicn.2011.37", "unstructured": "Atul Kumar Nishad and Rajeevan Chandel, “Analysis of Low Power High Performance XOR Gate using GDI Technique”,Conference, IEEE 2011 BIBLIOGRAPHY OF AUTHORS" } ], "record": { "registrant": "Longman Publishers", "registered": "2026-09-07", "updated": "2026-09-20", "issue_number": 1, "source": "crossref-api", "source_agency": "Crossref (member 25296)" } }, "url_after": "https://www.jst.org.in/index.php/pub/article/view/163", "sha256_before": "c3160c644734e1d16386e066c4700ca0d1e2e4e37306a29c8dc7e142bbb84ad5", "sha256_after": "c3a4a7bddfbb3d527fbd68032a3cb79166c2fdb97e7d7eef5f00bf385cdbca29" } ] }