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As part of this research effort, IDDT is being used to test for faults and issues in CMOS SRAM cells, and it is also being used to test for flaws and issues in CMOS SRAM cells as part of a separate study of the same name. In either case, a transient current pulse generated during a transition write operation or a transition read operation may be monitored for system failures, allowing them to be discovered and remedied. For the purpose of detecting and measuring the transient current pulse, it is required to design a circuit for monitoring current. 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As part of this research effort, IDDT is being used to test for faults and issues in CMOS SRAM cells, and it is also being used to test for flaws and issues in CMOS SRAM cells as part of a separate study of the same name. In either case, a transient current pulse generated during a transition write operation or a transition read operation may be monitored for system failures, allowing them to be discovered and remedied. For the purpose of detecting and measuring the transient current pulse, it is required to design a circuit for monitoring current. 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Figueras, J. Segura 1990, ―Quiescent current sensor circuits in digital VLSI CMOS testing‖, Electronic Letters, Vol. 26, pp. 1204- 120" }, { "key": "ref6", "doi": "10.1109/vtest.1996.510847", "unstructured": "Balachandran 1996, ―Improvement of SRAM-based failure analysis using calibrated Iddq testing‖ VLSI Test Symposium, Proceedings of 14th, IEEE pp. 130–136" }, { "key": "ref7", "doi": "10.5121/vlsic.2012.3309", "unstructured": "Sunil Jadav1, Vikrant2, Munish Vashisath June 2012 ―Design and performance analysis of ultra Low power 6t sram using adiabatic Technique‖ International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3" }, { "key": "ref8", "doi": "10.1109/mdt.2002.1033788", "unstructured": "R. Rodriquez 2002, ―Resistance Characterization of Interconnect Weak and Strong Open Defects‖, IEEE Design & Test of Computers, vol.19, n.5, Sept-, pp.18-26" }, { "key": "ref9", "doi": "10.1109/ats.2004.75", "unstructured": "Luigi Dilillo, Patrick Girard 2004 ―Resistive-Open Defects in Embedded-SRAM core cells: Analysis and March Test Solution‖ 13th Asian Test Symposium, Kenting, Taiwan Nov 15-17" }, { "key": "ref10", "doi": "10.1109/etsym.2010.5512768", "unstructured": "Fonseca 2010 ―Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes‖ Test Symposium (ETS), 15th IEEE European" }, { "key": "ref11", "doi": "10.1109/ats.2000.893615", "unstructured": "S. Hamdioui and A.J. Van De Goor, 2000 ―An Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests‖, Proc. of IEEE Asian Test Symposium, pp. 131-138" }, { "key": "ref12", "doi": "10.1109/date.2002.998473", "unstructured": "Suriya A. Kumar, Rafic Z. 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