{ "ok": true, "doi": "10.46243/jst.2020.v5.i4.pp199-207", "events": [ { "seq": 1, "kind": "register", "at": "2026-09-29 22:00:37", "by": "Administrator (admin)", "by_kind": "user", "note": "registered at Crossref; record read from api.crossref.org", "changes": [ { "path": "abstract.lang", "from": null, "to": "en" }, { "path": "abstract.value", "from": null, "to": "In the realm of Very Large Scale Integration (VLSI) circuit design, power efficiency has emerged as a paramount concern, particularly in the development of low-power electronic devices. This review paper delves into the efficacy of power gating techniques as a pivotal strategy to mitigate power consumption in VLSI circuits. We commence by elucidating the fundamental challenges associated with power consumption in VLSI circuits and introduce power gating as a viable solution. The paper systematically synthesizes existing literature, offering a comprehensive historical overview of power-saving methodologies in VLSI, with a specific focus on various power gating techniques. We critically analyze these techniques against key performance metrics such as leakage current reduction, delay, and area overhead, providing a comparative perspective. The review extends to recent advancements and innovative approaches in the field, highlighting their practical applications and effectiveness. Furthermore, we discuss the challenges and limitations inherent in current power gating designs, offering insights into potential areas for future research. This paper aims to serve as a resource for researchers and practitioners in the field of VLSI design, offering a detailed understanding of the current state of power gating techniques and their role in advancing low-power VLSI circuitry." }, { "path": "agents.0.name.family", "from": null, "to": "Srimannarayana Murthy" }, { "path": "agents.0.name.given", "from": null, "to": "Thirunahari" }, { "path": "agents.0.role", "from": null, "to": "author" }, { "path": "agents.0.sequence", "from": null, "to": "first" }, { "path": "agents.1.name.family", "from": null, "to": "ManojKuma" }, { "path": "agents.1.name.given", "from": null, "to": "Dr r" }, { "path": "agents.1.role", "from": null, "to": "author" }, { "path": "agents.1.sequence", "from": null, "to": "additional" }, { "path": "agents.2.name.org", "from": null, "to": "Longman Publishers" }, { "path": "agents.2.role", "from": null, "to": "publisher" }, { "path": "characters.0", "from": null, "to": "Language" }, { "path": "container.identifiers.0.medium", "from": null, "to": "electronic" }, { "path": "container.identifiers.0.type", "from": null, "to": "ISSN" }, { "path": "container.identifiers.0.value", "from": null, "to": "2456-5660" }, { "path": "container.issue", "from": null, "to": "04" }, { "path": "container.pages.first", "from": null, "to": "199" }, { "path": "container.pages.last", "from": null, "to": "207" }, { "path": "container.titles.0.type", "from": null, "to": "PrincipalTitle" }, { "path": "container.titles.0.value", "from": null, "to": "Journal of Science & Technology" }, { "path": "container.type", "from": null, "to": "Journal" }, { "path": "container.volume", "from": null, "to": "05" }, { "path": "dates.date_type", "from": null, "to": "PublicationDate" }, { "path": "dates.online", "from": null, "to": "2020-08-14" }, { "path": "dates.published", "from": null, "to": "2020-08-14" }, { "path": "doi", "from": null, "to": "10.46243/jst.2020.v5.i4.pp199-207" }, { "path": "format", "from": null, "to": "smartscholars-doi-metadata/1.0" }, { "path": "identifiers.0.type", "from": null, "to": "DOI" }, { "path": "identifiers.0.value", "from": null, "to": "10.46243/jst.2020.v5.i4.pp199-207" }, { "path": "language", "from": null, "to": "en" }, { "path": "license.applies_to", "from": null, "to": "vor" }, { "path": "license.start", "from": null, "to": "2020-08-14" }, { "path": "license.url", "from": null, "to": "https://creativecommons.org/licenses/by/4.0" }, { "path": "links.0.primary", "from": null, "to": true }, { "path": "links.0.return_type", "from": null, "to": "text/html" }, { "path": "links.0.url", "from": null, "to": "https://www.jst.org.in/index.php/pub/article/view/660" }, { "path": "links.1.purpose", "from": null, "to": "text-mining" }, { "path": "links.1.return_type", "from": null, "to": "application/pdf" }, { "path": "links.1.url", "from": null, "to": "https://www.jst.org.in/index.php/pub/article/download/660/588" }, { "path": "links.2.purpose", "from": null, "to": "text-mining" }, { "path": "links.2.return_type", "from": null, "to": "application/xml" }, { "path": "links.2.url", "from": null, "to": "https://www.jst.org.in/index.php/pub/article/download/660/3071" }, { "path": "links.3.purpose", "from": null, "to": "similarity-checking" }, { "path": "links.3.url", "from": null, "to": "https://www.jst.org.in/index.php/pub/article/view/660/588" }, { "path": "modes.0", "from": null, "to": "Visual" }, { "path": "record.issue_number", "from": null, "to": 1 }, { "path": "record.registered", "from": null, "to": "2026-09-10" }, { "path": "record.registrant", "from": null, "to": "Longman Publishers" }, { "path": "record.source", "from": null, "to": "crossref-api" }, { "path": "record.source_agency", "from": null, "to": "Crossref (member 25296)" }, { "path": "record.updated", "from": null, "to": "2026-09-20" }, { "path": "references.0.doi", "from": null, "to": "10.1109/icsccn.2011.6024639" }, { "path": "references.0.key", "from": null, "to": "ref1" }, { "path": "references.0.unstructured", "from": null, "to": "C. Suji, S. Maragatharaj, & R. Hemima. (2011). Performance analysis of power gating designs in low power VLSI circuits. Link" }, { "path": "references.1.key", "from": null, "to": "ref2" }, { "path": "references.1.unstructured", "from": null, "to": "R. Korah & N. Vijayan. Power Reduction In Logic Circuits Using Power Gating For Deep Sub-Micron CMOS VLSI" }, { "path": "references.10.doi", "from": null, "to": "10.1145/1835420.1835421" }, { "path": "references.10.key", "from": null, "to": "ref11" }, { "path": "references.10.unstructured", "from": null, "to": "Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, T. Sakurai, \"Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs,\" 2010. DOI: 10.1145/1835420.1835421" }, { "path": "references.11.doi", "from": null, "to": "10.1109/icccis56430.2022.10037651" }, { "path": "references.11.key", "from": null, "to": "ref12" }, { "path": "references.11.unstructured", "from": null, "to": "K. Annamma, Sobhit Saxena, G. Patel, \"Comparative analysis of low power leakage techniques implemented in different CMOS VLSI Circuits,\" 2022" }, { "path": "references.12.doi", "from": null, "to": "10.1109/dac.2002.1012673" }, { "path": "references.12.key", "from": null, "to": "ref13" }, { "path": "references.12.unstructured", "from": null, "to": "M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, “Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique,” in Proceedings of the 39th annual Design Automation Conference, 2002, pp. 480–485" }, { "path": "references.13.doi", "from": null, "to": "10.1109/jssc.1996.542322" }, { "path": "references.13.key", "from": null, "to": "ref14" }, { "path": "references.13.unstructured", "from": null, "to": "T. Kuroda et al., “A 0.9-V, 150-MHz, 10-mW, 4-mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1770–1779, Nov. 1996" }, { "path": "references.14.doi", "from": null, "to": "10.1109/4.400426" }, { "path": "references.14.key", "from": null, "to": "ref15" }, { "path": "references.14.unstructured", "from": null, "to": "S. Mutoh et al., “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 847–854, Aug. 1995" }, { "path": "references.15.doi", "from": null, "to": "10.1145/383082.383132" }, { "path": "references.15.key", "from": null, "to": "ref16" }, { "path": "references.15.unstructured", "from": null, "to": "S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, “Scaling of stack effect and its application for leakage reduction,” in Proceedings of the International Symposium on Low Power Electronics and Design, 2001, pp. 195–200" }, { "path": "references.2.key", "from": null, "to": "ref3" }, { "path": "references.2.unstructured", "from": null, "to": "Garima Gautam & R. Sikka. Low-Power Design of Digital VLSI Circuits. Link" }, { "path": "references.3.key", "from": null, "to": "ref4" }, { "path": "references.3.unstructured", "from": null, "to": "Teng Jing Ying & S. H. Ruslan. VLSI Implementation of Low Power Face Detection System" }, { "path": "references.4.doi", "from": null, "to": "10.1109/icsccn.2011.6024639" }, { "path": "references.4.key", "from": null, "to": "ref5" }, { "path": "references.4.unstructured", "from": null, "to": "C. Suji, S. Maragatharaj, & R. Hemima. (2011). Performance analysis of power gating designs in low power VLSI circuits. Link" }, { "path": "references.5.doi", "from": null, "to": "10.1007/978-81-322-2757-1_30" }, { "path": "references.5.key", "from": null, "to": "ref6" }, { "path": "references.5.unstructured", "from": null, "to": "G. Srikanth, Bhanu Murthy Bhaskara, & M. A. Rani. A Survey on Power Gating Techniques in Low Power VLSI Design. Link" }, { "path": "references.6.doi", "from": null, "to": "10.1088/1757-899x/1084/1/012058" }, { "path": "references.6.key", "from": null, "to": "ref7" }, { "path": "references.6.unstructured", "from": null, "to": "S. Pousia & K. Murugan. (2021). VLSI Implementation Of High Speed Low Power Design Using Hybrid Power Gating Technique. Link" }, { "path": "references.7.key", "from": null, "to": "ref8" }, { "path": "references.7.unstructured", "from": null, "to": "R. Korah & N. Vijayan. Power Reduction In Logic Circuits Using Power Gating For Deep Sub-Micron CMOS VLSI" }, { "path": "references.8.doi", "from": null, "to": "10.1109/icraie51050.2020.9358375" }, { "path": "references.8.key", "from": null, "to": "ref9" }, { "path": "references.8.unstructured", "from": null, "to": "Preeti Sahu, S. Agrahari, \"Comparative Analysis of Different Clock Gating Techniques,\" 2020. DOI: 10.1109/ICRAIE51050.2020.9358375" }, { "path": "references.9.key", "from": null, "to": "ref10" }, { "path": "references.9.unstructured", "from": null, "to": "Aditya Waingankar, Asha Waskar, Pratikkumar Rathod, Mahalaxmi Palinje, \"Comparative Analysis of VLSI circuits using multigate devices.\"" }, { "path": "referent", "from": null, "to": "Creation" }, { "path": "structural_type", "from": null, "to": "Digital" }, { "path": "titles.0.lang", "from": null, "to": "en" }, { "path": "titles.0.type", "from": null, "to": "PrincipalTitle" }, { "path": "titles.0.value", "from": null, "to": "Exploring Power Gating Strategies in VLSI Circuits: A Comparative Study and Technological Insights" }, { "path": "type", "from": null, "to": "JournalArticle" } ], "record_after": { "format": "smartscholars-doi-metadata/1.0", "doi": "10.46243/jst.2020.v5.i4.pp199-207", "referent": "Creation", "type": "JournalArticle", "structural_type": "Digital", "modes": [ "Visual" ], "characters": [ "Language" ], "titles": [ { "value": "Exploring Power Gating Strategies in VLSI Circuits: A Comparative Study and Technological Insights", "type": "PrincipalTitle", "lang": "en" } ], "identifiers": [ { "type": "DOI", "value": "10.46243/jst.2020.v5.i4.pp199-207" } ], "agents": [ { "role": "author", "name": { "given": "Thirunahari", "family": "Srimannarayana Murthy" }, "sequence": "first" }, { "role": "author", "name": { "given": "Dr r", "family": "ManojKuma" }, "sequence": "additional" }, { "role": "publisher", "name": { "org": "Longman Publishers" } } ], "dates": { "published": "2020-08-14", "date_type": "PublicationDate", "online": "2020-08-14" }, "language": "en", "container": { "type": "Journal", "titles": [ { "value": "Journal of Science & Technology", "type": "PrincipalTitle" } ], "identifiers": [ { "type": "ISSN", "value": "2456-5660", "medium": "electronic" } ], "volume": "05", "issue": "04", "pages": { "first": "199", "last": "207" } }, "links": [ { "url": "https://www.jst.org.in/index.php/pub/article/view/660", "return_type": "text/html", "primary": true }, { "url": "https://www.jst.org.in/index.php/pub/article/download/660/588", "purpose": "text-mining", "return_type": "application/pdf" }, { "url": "https://www.jst.org.in/index.php/pub/article/download/660/3071", "purpose": "text-mining", "return_type": "application/xml" }, { "url": "https://www.jst.org.in/index.php/pub/article/view/660/588", "purpose": "similarity-checking" } ], "abstract": { "value": "In the realm of Very Large Scale Integration (VLSI) circuit design, power efficiency has emerged as a paramount concern, particularly in the development of low-power electronic devices. This review paper delves into the efficacy of power gating techniques as a pivotal strategy to mitigate power consumption in VLSI circuits. We commence by elucidating the fundamental challenges associated with power consumption in VLSI circuits and introduce power gating as a viable solution. The paper systematically synthesizes existing literature, offering a comprehensive historical overview of power-saving methodologies in VLSI, with a specific focus on various power gating techniques. We critically analyze these techniques against key performance metrics such as leakage current reduction, delay, and area overhead, providing a comparative perspective. The review extends to recent advancements and innovative approaches in the field, highlighting their practical applications and effectiveness. Furthermore, we discuss the challenges and limitations inherent in current power gating designs, offering insights into potential areas for future research. This paper aims to serve as a resource for researchers and practitioners in the field of VLSI design, offering a detailed understanding of the current state of power gating techniques and their role in advancing low-power VLSI circuitry.", "lang": "en" }, "license": { "url": "https://creativecommons.org/licenses/by/4.0", "start": "2020-08-14", "applies_to": "vor" }, "references": [ { "key": "ref1", "doi": "10.1109/icsccn.2011.6024639", "unstructured": "C. Suji, S. Maragatharaj, & R. Hemima. (2011). Performance analysis of power gating designs in low power VLSI circuits. Link" }, { "key": "ref2", "unstructured": "R. Korah & N. Vijayan. Power Reduction In Logic Circuits Using Power Gating For Deep Sub-Micron CMOS VLSI" }, { "key": "ref3", "unstructured": "Garima Gautam & R. Sikka. Low-Power Design of Digital VLSI Circuits. Link" }, { "key": "ref4", "unstructured": "Teng Jing Ying & S. H. Ruslan. VLSI Implementation of Low Power Face Detection System" }, { "key": "ref5", "doi": "10.1109/icsccn.2011.6024639", "unstructured": "C. Suji, S. Maragatharaj, & R. Hemima. (2011). Performance analysis of power gating designs in low power VLSI circuits. Link" }, { "key": "ref6", "doi": "10.1007/978-81-322-2757-1_30", "unstructured": "G. Srikanth, Bhanu Murthy Bhaskara, & M. A. Rani. A Survey on Power Gating Techniques in Low Power VLSI Design. Link" }, { "key": "ref7", "doi": "10.1088/1757-899x/1084/1/012058", "unstructured": "S. Pousia & K. Murugan. (2021). VLSI Implementation Of High Speed Low Power Design Using Hybrid Power Gating Technique. Link" }, { "key": "ref8", "unstructured": "R. Korah & N. Vijayan. Power Reduction In Logic Circuits Using Power Gating For Deep Sub-Micron CMOS VLSI" }, { "key": "ref9", "doi": "10.1109/icraie51050.2020.9358375", "unstructured": "Preeti Sahu, S. Agrahari, \"Comparative Analysis of Different Clock Gating Techniques,\" 2020. DOI: 10.1109/ICRAIE51050.2020.9358375" }, { "key": "ref10", "unstructured": "Aditya Waingankar, Asha Waskar, Pratikkumar Rathod, Mahalaxmi Palinje, \"Comparative Analysis of VLSI circuits using multigate devices.\"" }, { "key": "ref11", "doi": "10.1145/1835420.1835421", "unstructured": "Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, T. Sakurai, \"Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs,\" 2010. DOI: 10.1145/1835420.1835421" }, { "key": "ref12", "doi": "10.1109/icccis56430.2022.10037651", "unstructured": "K. Annamma, Sobhit Saxena, G. Patel, \"Comparative analysis of low power leakage techniques implemented in different CMOS VLSI Circuits,\" 2022" }, { "key": "ref13", "doi": "10.1109/dac.2002.1012673", "unstructured": "M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, “Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique,” in Proceedings of the 39th annual Design Automation Conference, 2002, pp. 480–485" }, { "key": "ref14", "doi": "10.1109/jssc.1996.542322", "unstructured": "T. Kuroda et al., “A 0.9-V, 150-MHz, 10-mW, 4-mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1770–1779, Nov. 1996" }, { "key": "ref15", "doi": "10.1109/4.400426", "unstructured": "S. Mutoh et al., “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 847–854, Aug. 1995" }, { "key": "ref16", "doi": "10.1145/383082.383132", "unstructured": "S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, “Scaling of stack effect and its application for leakage reduction,” in Proceedings of the International Symposium on Low Power Electronics and Design, 2001, pp. 195–200" } ], "record": { "registrant": "Longman Publishers", "registered": "2026-09-10", "updated": "2026-09-20", "issue_number": 1, "source": "crossref-api", "source_agency": "Crossref (member 25296)" } }, "url_after": "https://www.jst.org.in/index.php/pub/article/view/660", "sha256_before": null, "sha256_after": "fdd10f5db187af3f1f7c43979dea7706f9533170c054481545a3c4e9ffa45070" }, { "seq": 2, "kind": "update", "at": "2026-09-29 23:59:57", "by": "Administrator (admin)", "by_kind": "user", "note": "record re-read from api.crossref.org", "changes": [ { "path": "container.titles.0.value", "from": "Journal of Science & Technology", "to": "Journal of Science & Technology" } ], "record_after": { "format": "smartscholars-doi-metadata/1.0", "doi": "10.46243/jst.2020.v5.i4.pp199-207", "referent": "Creation", "type": "JournalArticle", "structural_type": "Digital", "modes": [ "Visual" ], "characters": [ "Language" ], "titles": [ { "value": "Exploring Power Gating Strategies in VLSI Circuits: A Comparative Study and Technological Insights", "type": "PrincipalTitle", "lang": "en" } ], "identifiers": [ { "type": "DOI", "value": "10.46243/jst.2020.v5.i4.pp199-207" } ], "agents": [ { "role": "author", "name": { "given": "Thirunahari", "family": "Srimannarayana Murthy" }, "sequence": "first" }, { "role": "author", "name": { "given": "Dr r", "family": "ManojKuma" }, "sequence": "additional" }, { "role": "publisher", "name": { "org": "Longman Publishers" } } ], "dates": { "published": "2020-08-14", "date_type": "PublicationDate", "online": "2020-08-14" }, "language": "en", "container": { "type": "Journal", "titles": [ { "value": "Journal of Science & Technology", "type": "PrincipalTitle" } ], "identifiers": [ { "type": "ISSN", "value": "2456-5660", "medium": "electronic" } ], "volume": "05", "issue": "04", "pages": { "first": "199", "last": "207" } }, "links": [ { "url": "https://www.jst.org.in/index.php/pub/article/view/660", "return_type": "text/html", "primary": true }, { "url": "https://www.jst.org.in/index.php/pub/article/download/660/588", "purpose": "text-mining", "return_type": "application/pdf" }, { "url": "https://www.jst.org.in/index.php/pub/article/download/660/3071", "purpose": "text-mining", "return_type": "application/xml" }, { "url": "https://www.jst.org.in/index.php/pub/article/view/660/588", "purpose": "similarity-checking" } ], "abstract": { "value": "In the realm of Very Large Scale Integration (VLSI) circuit design, power efficiency has emerged as a paramount concern, particularly in the development of low-power electronic devices. This review paper delves into the efficacy of power gating techniques as a pivotal strategy to mitigate power consumption in VLSI circuits. We commence by elucidating the fundamental challenges associated with power consumption in VLSI circuits and introduce power gating as a viable solution. The paper systematically synthesizes existing literature, offering a comprehensive historical overview of power-saving methodologies in VLSI, with a specific focus on various power gating techniques. We critically analyze these techniques against key performance metrics such as leakage current reduction, delay, and area overhead, providing a comparative perspective. The review extends to recent advancements and innovative approaches in the field, highlighting their practical applications and effectiveness. Furthermore, we discuss the challenges and limitations inherent in current power gating designs, offering insights into potential areas for future research. This paper aims to serve as a resource for researchers and practitioners in the field of VLSI design, offering a detailed understanding of the current state of power gating techniques and their role in advancing low-power VLSI circuitry.", "lang": "en" }, "license": { "url": "https://creativecommons.org/licenses/by/4.0", "start": "2020-08-14", "applies_to": "vor" }, "references": [ { "key": "ref1", "doi": "10.1109/icsccn.2011.6024639", "unstructured": "C. Suji, S. Maragatharaj, & R. Hemima. (2011). Performance analysis of power gating designs in low power VLSI circuits. Link" }, { "key": "ref2", "unstructured": "R. Korah & N. Vijayan. Power Reduction In Logic Circuits Using Power Gating For Deep Sub-Micron CMOS VLSI" }, { "key": "ref3", "unstructured": "Garima Gautam & R. Sikka. Low-Power Design of Digital VLSI Circuits. Link" }, { "key": "ref4", "unstructured": "Teng Jing Ying & S. H. Ruslan. VLSI Implementation of Low Power Face Detection System" }, { "key": "ref5", "doi": "10.1109/icsccn.2011.6024639", "unstructured": "C. Suji, S. Maragatharaj, & R. Hemima. (2011). Performance analysis of power gating designs in low power VLSI circuits. Link" }, { "key": "ref6", "doi": "10.1007/978-81-322-2757-1_30", "unstructured": "G. Srikanth, Bhanu Murthy Bhaskara, & M. A. Rani. A Survey on Power Gating Techniques in Low Power VLSI Design. Link" }, { "key": "ref7", "doi": "10.1088/1757-899x/1084/1/012058", "unstructured": "S. Pousia & K. Murugan. (2021). VLSI Implementation Of High Speed Low Power Design Using Hybrid Power Gating Technique. Link" }, { "key": "ref8", "unstructured": "R. Korah & N. Vijayan. Power Reduction In Logic Circuits Using Power Gating For Deep Sub-Micron CMOS VLSI" }, { "key": "ref9", "doi": "10.1109/icraie51050.2020.9358375", "unstructured": "Preeti Sahu, S. Agrahari, \"Comparative Analysis of Different Clock Gating Techniques,\" 2020. DOI: 10.1109/ICRAIE51050.2020.9358375" }, { "key": "ref10", "unstructured": "Aditya Waingankar, Asha Waskar, Pratikkumar Rathod, Mahalaxmi Palinje, \"Comparative Analysis of VLSI circuits using multigate devices.\"" }, { "key": "ref11", "doi": "10.1145/1835420.1835421", "unstructured": "Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, T. Sakurai, \"Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs,\" 2010. DOI: 10.1145/1835420.1835421" }, { "key": "ref12", "doi": "10.1109/icccis56430.2022.10037651", "unstructured": "K. Annamma, Sobhit Saxena, G. Patel, \"Comparative analysis of low power leakage techniques implemented in different CMOS VLSI Circuits,\" 2022" }, { "key": "ref13", "doi": "10.1109/dac.2002.1012673", "unstructured": "M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, “Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique,” in Proceedings of the 39th annual Design Automation Conference, 2002, pp. 480–485" }, { "key": "ref14", "doi": "10.1109/jssc.1996.542322", "unstructured": "T. Kuroda et al., “A 0.9-V, 150-MHz, 10-mW, 4-mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1770–1779, Nov. 1996" }, { "key": "ref15", "doi": "10.1109/4.400426", "unstructured": "S. Mutoh et al., “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 847–854, Aug. 1995" }, { "key": "ref16", "doi": "10.1145/383082.383132", "unstructured": "S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, “Scaling of stack effect and its application for leakage reduction,” in Proceedings of the International Symposium on Low Power Electronics and Design, 2001, pp. 195–200" } ], "record": { "registrant": "Longman Publishers", "registered": "2026-09-10", "updated": "2026-09-20", "issue_number": 1, "source": "crossref-api", "source_agency": "Crossref (member 25296)" } }, "url_after": "https://www.jst.org.in/index.php/pub/article/view/660", "sha256_before": "fdd10f5db187af3f1f7c43979dea7706f9533170c054481545a3c4e9ffa45070", "sha256_after": "f2b6e221d6853f40212a057c994331b5f0e48e43f7aa35245c5ae597b0c2cffb" } ] }